Takeo YAMASHITA


Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design
Norio OHKUBO Takeo YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 618-623
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
delay calculationeffective capacitancelogic circuit optimizationdelay optimizationLSI design
 Summary | Full Text:PDF(636.3KB)

Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS
Naoki KATO Yohei AKITA Mitsuru HIRAKI Takeo YAMASHITA Teruhisa SHIMIZU Fuyuhiko MAKI Kazuo YANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1747-1754
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
CMOSthreshold voltageleakage currentlow power
 Summary | Full Text:PDF(1.2MB)

Minimizing the Edge Effect in a DRAM Cell Capacitor by Using a Structure with High-Permittivity Thin Film
Takeo YAMASHITA Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4  pp. 556-561
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
suppression of edge effecthigh permittivity materialsimplified DRAM cell capacitorhigh density DRAMs
 Summary | Full Text:PDF(497.6KB)

Plasma-Parameter-Extraction for Minimizing Contamination and Damage in RIE Processes
Takeo YAMASHITA Satoshi HASAKA Iwao NATORI Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/07/25
Vol. E75-C  No. 7  pp. 839-843
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra Clean Technology)
Category: 
Keyword: 
ion energyion fluxcontaminationion energy-flux parameter map
 Summary | Full Text:PDF(459KB)