Takenori KOUDA


Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2554-2562
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic optimizationFPGAsSPFDsPSPFDs
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