Takehiko NAKAO


The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI
Takehiko NAKAO Masanori KUWAHARA Yasuo OHARA Reiji ARIYOSHI Toshihiko KITAZUME Naoki SUGAWA Takeshi OGAWARA Satoshi ODA Shoji NOMURA Yuichi MIYAZAWA Akira KANUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 746-749
Type of Manuscript:  Special Section LETTER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
PLLjitterATMQPLC
 Summary | Full Text:PDF(277.6KB)

A 110-MHz/1-Mb Synchronous TagRAM
Yasuo UNEKAWA Tsuguo KOBAYASHI Tsukasa SHIROTORI Yukihiro FUJIMOTO Takayoshi SHIMAZAWA Kazutaka NOGAMI Takehiko NAKAO Kazuhiro SAWADA Masataka MATSUI Takayasu SAKURAI Man Kit TANG William A. HUFFMAN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 733-740
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(743.6KB)