Takashi OHSAWA


A New Read Scheme for High-Density Emerging Memories
Takashi OHSAWA 
Publication:   
Publication Date: 2018/06/01
Vol. E101-C  No. 6  pp. 423-429
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ReRAMSTT-MRAMPCRAMmemristorreference celldummy cellredundancybit yieldweighted average
 Summary | Full Text:PDF(1.1MB)

Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating
Shuta TOGASHI Takashi OHSAWA Tetsuo ENDOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5  pp. 854-859
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
MTJnonvolatilefine-grained power gatingcounter unitlow power
 Summary | Full Text:PDF(1.6MB)

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
 Summary | Full Text:PDF(803.3KB)

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMpower dissipationreliabilitybit-linewordlinesmall swingthreshold voltagesense amplifiermemory cell
 Summary | Full Text:PDF(772.8KB)