Takashi NAKADA

Development of High Power-Efficient Processor with Linear FU Array Accelerator
Mitsutoshi SAITO  Shunsuke SHITAOKA  Devisetti VENKATA RAMA NAVEEN  Suguru OUE  Kazuhiro YOSHIMURA  Jun YAO  Takashi NAKADA  Yasuhiko NAKASHIMA 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2012/09/01
Vol. J95-D  No. 9  pp. 1729-1737
Type of Manuscript: PAPER
Category: 
Keyword: 
FU array,  processor development,  LSI prototyping, 
  Summary |  Full Text(in Japanese):PDF (943.5KB)
Development of a Power Efficient SMT Processor with Heterogeneous Instruction Set Architectures
Kazuhiro YOSHIMURA  Takashi NAKADA  Yasuhiko NAKASHIMA  Toshiaki KITAMURA 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2012/06/01
Vol. J95-D  No. 6  pp. 1334-1346
Type of Manuscript: PAPER
Category: 
Keyword: 
VLIW/superscalar mixed architecture,  multithreading,  LSI prototyping,  processor development environment, 
  Summary |  Full Text(in Japanese):PDF (1022.7KB)
A Method of Reducing Communication Costs for Parallel Simulations of Quantum Computation
Akihiro SHIBATA  Takashi NAKADA  Masaki NAKANISHI  Shigeru YAMASHITA  Yasuhiko NAKASHIMA 
Publication:   D - Abstracts of IEICE TRANSACTIONS on Information and Systems (Japanese Edition)
Publication Date: 2010/03/01
Vol. J93-D  No. 3  pp. 253-264
Type of Manuscript: PAPER
Category: 
Keyword: 
quantum computer,  quantum computer simulations,  quantum circuit,  swap gate,  distributed memory parallel computers, 
  Summary |  Full Text(in Japanese):PDF (540.2KB)