Takashi KAMBE


Hardware Algorithm Optimization Using Bach C
Kazuhisa OKADA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4  pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high level synthesisbehavioral synthesisC languageBach C
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FOREWORD
Yukihiro NAKAMURA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2399-2399
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(210.9KB)

A Cell Synthesis Method for Salicide Process Using Assignment Graph
Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2577-2583
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Synthesis
Keyword: 
celllayoutsynthesissalicideassignment graph
 Summary | Full Text:PDF(581.5KB)

Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes
Mizuki TAKAHASHI Nagisa ISHIURA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2456-2463
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design and High-level Synthesis
Keyword: 
behavioral partitioningthread compositionbehavioral synthesis
 Summary | Full Text:PDF(671.1KB)

A Binding Algorithm for Retargetable Compilation to Non-orthogonal DSP Architectures
Masayuki YAMAGUCHI Nagisa ISHIURA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2630-2639
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
retargetable compilerbindingnon-orthogonal architectureDSPbinary decision diagram
 Summary | Full Text:PDF(869.9KB)

Register-Transfer Level Testability Analysis and Its Application to Design for Testability
Mizuki TAKAHASHI Ryoji SAKURAI Hiroaki NODA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2646-2654
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testability analysisregister transfer leveldesign for testability
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Rectilinear Shape Formation Method on Block Placement
Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/25
Vol. E81-A  No. 3  pp. 446-454
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
floorplanrectilinearsoft blockplacement
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Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Masayuki YAMAGUCHI Akihisa YAMADA Toshihiro NAKAOKA Takashi KAMBE Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1853-1860
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance evaluationdatapathstructureparallel constraint
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Datapath Scheduling for Behavioral Description with Conditional Branches
Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 1999-2009
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesisdatapath scheduling0-1 integer programming problembinary decision diagrambranch-and-bound method
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A Routing Method for Macro Cell VLSI Layout
Takashi KAMBE Tokihito OKADA Shin-ichi FUJIWARA Chiyoshi YOSHIOKA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/12/25
Vol. E73-E  No. 12  pp. 1979-1988
Type of Manuscript:  Special Section PAPER (Special Issue on the 3rd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design
Keyword: 
 Summary | Full Text:PDF(824.9KB)

A Floorplanning Scheme of VLSI Design
Takashi KAMBE Tuneo TOMITA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/12/25
Vol. E71-E  No. 12  pp. 1236-1242
Type of Manuscript:  Special Section PAPER (Special Issue on CAS Karuizawa Workshop)
Category: 
Keyword: 
 Summary | Full Text:PDF(521.1KB)