Takashi HIRAYAMA


A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits
Takashi HIRAYAMA Hayato SUGAWARA Katsuhisa YAMANAKA Yasuaki NISHITANI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2253-2261
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Reversible/Quantum Computing
Keyword: 
reversible logic circuitsToffoli gateslower boundlogic minimization
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New Three-Level Boolean Expression Based on EXOR Gates
Ryoji ISHIKAWA Takashi HIRAYAMA Goro KODA Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/05/01
Vol. E87-D  No. 5  pp. 1214-1222
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
EXOR gatesthree-level logicpseudoproductcompact designtestability
 Summary | Full Text:PDF(655.1KB)

A Faster Algorithm of Minimizing AND-EXOR Expressions
Takashi HIRAYAMA Yasuaki NISHITANI Toru SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2708-2714
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
AND-EXOR two-level circuitAND-EXOR expressionexclusive-or sum-of-products expressionlogic minimization algorithm
 Summary | Full Text:PDF(239.1KB)

Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
Takashi HIRAYAMA Goro KODA Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/09/25
Vol. E82-D  No. 9  pp. 1278-1286
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
logic synthesisexclusive-orsingle stuck-at faulteasily testable realization
 Summary | Full Text:PDF(861.2KB)

Minimization of AND-EXOR Expressions for Symmetric Functions
Takashi HIRAYAMA Yasuaki NISHITANI Kensuke SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 567-570
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
logic synthesisAND-EXOR expressionsymmetric functionlogic minimization algorithm
 Summary | Full Text:PDF(351.3KB)