Takao WATANABE


The Umbrella Cell: A High-Density 2T Cell for SOC Applications
Satoru AKIYAMA Takao WATANABE Nobuhiro OODAIRA Tsuyoshi ISHIKAWA Digh HISAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 614-621
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
SOCon-chip memorylow-voltageplanar capacitorlogic-process
 Summary | Full Text:PDF(1.1MB)

Low-Power and High-Speed Advantages of DRAM-Logic Integration for Multimedia Systems
Takao WATANABE Ryo FUJITA Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1523-1531
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
DRAM-integrated chipembedded DRAMcomputer graphicsmain memory
 Summary | Full Text:PDF(703.7KB)

3-D CG Media Chip: An Experimental Single-Chip Architecture for Three-Dimensional Computer Graphics
Takao WATANABE Kazushige AYUKAWA Yoshinobu NAKAGOME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12  pp. 1881-1887
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword: 
media chipDRAM3-D computer graphics1.5-V operation0.35-µm CMOS design rule
 Summary | Full Text:PDF(614.5KB)

The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
Takao WATANABE Masakazu AOKI Katsutaka KIMURA Takeshi SAKATA Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1206-1214
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
DRAM-based neuro-chip106-synapse neural network1.5-V digital chip0.5-µm CMOS design rule
 Summary | Full Text:PDF(817.2KB)