Takako ISHIHARA


A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications
Nobutaro SHIBATA Mayumi WATANABE Takako ISHIHARA 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11  pp. 1061-1068
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
10T memory cellCMOSdual-port SRAMFIFO memoryfully depleted SOIlook-ahead operationmulti-VDDserial access
 Summary | Full Text:PDF(1MB)

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications
Nobutaro SHIBATA Yoshinori GOTOH Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 717-726
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
10T typebitline capacitanceCMOSgate arrayhigh speedlow powermemory-oriented base cellshared contacttwo-port SRAM
 Summary | Full Text:PDF(1.7MB)

A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme
Nobutaro SHIBATA Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C  No. 2  pp. 316-330
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
4-way set-associativecache-tagCMOSdirected graphdual-rail wordlineFD-SOII/O-separated memory cellLRUNRZ-type write-enable signalSIMOXSRAM
 Summary | Full Text:PDF(1.5MB)

EB-Testing-Pad Method and its Evaluation by Actual Devices
Norio KUJI Takako ISHIHARA Shigeru NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1558-1563
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
Keyword: 
E-beam testerobservabilitystacked viastesting padsmulti level wiring
 Summary | Full Text:PDF(626.7KB)