Takahiro WATANABE


High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem
Xin JIANG Xiangyang LEI Lian ZENG Takahiro WATANABE 
Publication:   
Publication Date: 2017/11/01
Vol. E100-A  No. 11  pp. 2379-2391
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
thermal-awarerouting algorithmfully adaptive3D NoC
 Summary | Full Text:PDF(3.8MB)

A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs
Tieyuan PAN Lian ZENG Yasuhiro TAKASHIMA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2412-2424
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
fast MER enumerationFPGAslow memory consumption
 Summary | Full Text:PDF(1.7MB)

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device
Tieyuan PAN Li ZHU Lian ZENG Takahiro WATANABE Yasuhiro TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1345-1354
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
online task placementreconfigurable deviceefficient data structureMER enumeration
 Summary | Full Text:PDF(2.2MB)

An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip
Lian ZENG Tieyuan PAN Xin JIANG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1334-1344
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
adaptive routingdeadlock-freecongestion-balancepath diversity3D network-on-chip
 Summary | Full Text:PDF(2.6MB)

Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2199-2207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
FPGAlow powerswitch boxrouting
 Summary | Full Text:PDF(4.3MB)

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2  pp. 314-323
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGAlow powerregionhierarchical designpower consumption
 Summary | Full Text:PDF(570.9KB)

A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction
Jiongyao YE Yu WAN Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2639-2648
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
misprediction recoverycritical path predictiontrace cache
 Summary | Full Text:PDF(743.4KB)

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2519-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
FPGAlow powerpower domainpower consumption
 Summary | Full Text:PDF(7.7MB)

An Adaptive Various-Width Data Cache for Low Power Design
Jiongyao YE Yu WAN Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/08/01
Vol. E94-D  No. 8  pp. 1539-1546
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
low powerdata cachefrequent valuesnarrow-width values
 Summary | Full Text:PDF(759.8KB)

Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism
Jiongyao YE Yingtao HU Hongfeng DING Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7  pp. 1398-1408
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
low powerinstruction cacheinstruction fetch mechanism
 Summary | Full Text:PDF(951.6KB)

Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover
Zhiguo BAO Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A  No. 1  pp. 281-290
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
genetic algorithmevolutionary algorithmscircuit optimizationevolutionary circuit designevolvable hardware
 Summary | Full Text:PDF(614.1KB)

Score Sequence Pair Problems of (r11, r12, r22)-Tournaments--Determination of Realizability--
Masaya TAKAHASHI Takahiro WATANABE Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/02/01
Vol. E90-D  No. 2  pp. 440-448
Type of Manuscript:  Special Section PAPER (Special Section on Foundations of Computer Science)
Category: Graph Algorithms
Keyword: 
algorithmgraph theoryprescribed degreesscore sequencetournament
 Summary | Full Text:PDF(446.7KB)

A Fine Grain Cooled Logic Architecture for Low-Power Processors
Hiroyuki MATSUBARA Takahiro WATANABE Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 735-740
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-powerpass transistordual-rail logicover-lapped clockCooled Logic
 Summary | Full Text:PDF(1MB)

A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
Hiroyuki MATSUBARA Takahiro WATANABE Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11  pp. 1733-1738
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
low-powerlevelingdynamic logicover-lapped clockpower control
 Summary | Full Text:PDF(837.6KB)

A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm
Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3  pp. 345-352
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
branch-and-boundlayoutglobal routingchannel-intersection graphanalogLSICAD
 Summary | Full Text:PDF(636.8KB)

A Framework for Feature Extraction of Images by Energy Minimization
Satoshi NAKAGAWA Takahiro WATANABE Yuji KUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/11/25
Vol. E77-D  No. 11  pp. 1213-1218
Type of Manuscript:  Special Section PAPER (Special Issue on Computer Vision)
Category: 
Keyword: 
active contour modelenergy minimizationmultiple imagesmotion trackingstereo matching
 Summary | Full Text:PDF(650.8KB)

Analog Layout Compaction with a Clean-up Function
Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/12/25
Vol. E71-E  No. 12  pp. 1243-1252
Type of Manuscript:  Special Section PAPER (Special Issue on CAS Karuizawa Workshop)
Category: 
Keyword: 
 Summary | Full Text:PDF(754.1KB)