IEICE SEARCH SYSTEM

Tadayoshi HORITA

Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant Tadayoshi HORITA Itsuo TAKANAMI Masatoshi MORI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/04/01 Vol. E91-D No. 4 pp. 1168-1175 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: multilayer neural network, fault-tolerance, weight fault, neuron fault, multiple fault,
	Summary \| Full Text:PDF (290.7KB)

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches Tadayoshi HORITA Yuuji KATOU Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 pp. 623-632 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: 3D mesh-connected processor arrays, 1.5-track switches, reconfiguration, fault tolerance, redundancy,
	Summary \| Full Text:PDF (758.7KB)

An Efficiently Self-Reconstructing Array System Using E-1-Track Switches Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2743-2752 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: mesh-connected processor arrays, 1-track switches, E-1-track switches, fault-tolerance, reconfigurable architecture,
	Summary \| Full Text:PDF (776.2KB)

A System for Efficiently Self-Reconstructing 1(1/2)-Track Switch Torus Arrays Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/12/01 Vol. E84-D No. 12 pp. 1801-1809 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: reconfiguration, 1(1/2)-track switch torus array, fault tolerance, wafer scale integration, self-reconfigurable system,
	Summary \| Full Text:PDF (790.8KB)

An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/08/20 Vol. E83-D No. 8 pp. 1701-1705 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: fault tolerant processor arrays, 1 1/2 track-switch model, self-reconfigurable system, run-time fault tolerance, wafer scale integration,
	Summary \| Full Text:PDF (664.5KB)

An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/12/20 Vol. E82-D No. 12 pp. 1545-1553 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: mesh-connected parallel computer, wafer scale integration, yield enhancement, fault tolerance, 1 1/2 track-switch model,
	Summary \| Full Text:PDF (965.5KB)

A Built-in Self-Reconfigurable Scheme for 3D Mesh Arrays Itsuo TAKANAMI Tadayoshi HORITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/12/20 Vol. E82-D No. 12 pp. 1554-1562 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault tolerance, reconstruction, three-dimensional mesh array, self-reconstruction, hardware algorithm,
	Summary \| Full Text:PDF (41.2KB)

Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits Itsuo TAKANAMI Satoru NAKAMURA Tadayoshi HORITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1678-1686 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Configurable Computing and Fault Tolerance Keyword: fault tolerance, three-dimensional mesh array, self-reconstruction, neural algorithm, neural circuit,
	Summary \| Full Text:PDF (943.7KB)

An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/09/20 Vol. E80-D No. 9 pp. 879-885 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Fault Tolerance Keyword: mesh-array, defect tolerance, link fault, PE fault, wafer scale integration,
	Summary \| Full Text:PDF (516.2KB)

A Built-In Self-Reconstruction Approach for Partitioned Mesh-Arrays Using Neural Algorithm Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/08/20 Vol. E79-D No. 8 pp. 1160-1167 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Fault Diagnosis/Tolerance Keyword: mesh-array, fault tolerance, self-reconfigurable system, wafer scale integration, neural algorithm,
	Summary \| Full Text:PDF (559.4KB)