Shyue-Kung LU


A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Widiant Masaki HASHIZUME Shohei SUENAGA Hiroyuki YOTSUYANAGI Akira ONO Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11  pp. 2723-2733
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
electrical testbuilt-in test circuitopen defectinterconnect testdesign for testability
 Summary | Full Text:PDF(2.5MB)

An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs
Tsu-Lin LI Masaki HASHIZUME Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 2026-2030
Type of Manuscript:  Special Section LETTER (Special Section on Dependable Computing)
Category: 
Keyword: 
NROMdata inversionfault maskingyield
 Summary | Full Text:PDF(573.4KB)

Defect Level Prediction Using Multi-Model Fault Coverage
Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/06/01
Vol. E87-D  No. 6  pp. 1488-1495
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
defect levelfault coveragemulti-model fault coverageyield
 Summary | Full Text:PDF(455.5KB)

Delay Fault Testing for CMOS Iterative Logic Arrays with a Constant Number of Patterns
Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2659-2665
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
delay faultIterative Logic ArrayC-testablebijection
 Summary | Full Text:PDF(742KB)