Shuzo YAJIMA


Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division
Takashi HORIYAMA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/08/25
Vol. E81-D  No. 8  pp. 793-800
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
Boolean functiondivisionbinary decision diagramslower boundfooling set
 Summary | Full Text:PDF(668.3KB)

Manipulation of Large-Scale Polynomials Using BMDs
Dror ROTTER Kiyoharu HAMAGUCHI Shin-ichi MINATO Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1774-1781
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
zero-suppressed binary decision diagrams (BDD)binary moment diagramspolynomials
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Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses
Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4  pp. 663-669
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computational complexityBoolean functionordered binary decision diagramsatisfiabilitycombinational circuitcutwidthsum-of-product formzero-suppressed binary decision diagrams (BDD)ternary decision diagram
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Formal Design Verification of Combinational Circuits Specified by Recurrence Equations
Hiroyuki OCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1431-1435
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design Verification
Keyword: 
formal design verificationbinary decision diagramarithmetic circuitsspecificationrecurrence equations
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The Complexity of the Optimal Variable Ordering Problems of a Shared Binary Decision Diagram
Seiichiro TANI Kiyoharu HAMAGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4  pp. 271-281
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
ordered binary decision diagramvariable orderingoptimal linear arrangementNP-completeBoolean function
 Summary | Full Text:PDF(924.5KB)

On the Computational Power of Binary Decision Diagrams
Hiroshi SAWADA Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/06/25
Vol. E77-D  No. 6  pp. 611-618
Type of Manuscript:  PAPER
Category: Automata, Languages and Theory of Computing
Keyword: 
binary decision diagramon-line Turing machineplaner circuitpermutationcomplete language
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Computational Complexity of Manipulating Binary Decision Diagrams
Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/06/25
Vol. E77-D  No. 6  pp. 642-647
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
binary decision diagramcomputatioal complexityBoolean functionparallel algorithm
 Summary | Full Text:PDF(554.8KB)

Compact Test Sequences for Scan-Based Sequential Circuits
Hiroyuki HIGUCHI Kiyoharu HAMAGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1676-1683
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test generationscan designtest application timeboolean function manipulation
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Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1121-1127
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
test generationcombinational circuitscompact test setsbinary decision diagrams
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Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic
Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1220-1229
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
design verificationsequential machinestemporal logicmodel checkingbinary decision diagram
 Summary | Full Text:PDF(786KB)

Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits
Nagisa ISHIURA Yutaka DEGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1247-1254
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic circuitstiming verificationsymbolic simulationBoolean function manipulation
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Linear Time Fault Simulation Algorithm Using a Content Addressable Memory
Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 314-320
Type of Manuscript:  INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
fault simulationcontent addressable memoryparallel computation
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Computational Power of Memory-Based Parallel Computation Models with Communication
Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/01/25
Vol. E75-D  No. 1  pp. 89-94
Type of Manuscript:  Special Section PAPER (Special Section on Theoretical Foundations of Computing)
Category: 
Keyword: 
parallel computation modelcomputational powerhypercube networkfunctional memorymemory-based parallel computation
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Properties of Embedded Multivalued Dependencies in Relational Databases
Katsumi TANAKA Yahiko KAMBAYASHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1979/08/25
Vol. E62-E  No. 8  pp. 536-543
Type of Manuscript:  PAPER
Category: Data Processing
Keyword: 
 Summary | Full Text:PDF(683.8KB)

Reshaping of Power Spectra of Digital Coded Signals by Restricting Inputs to Encoding Automata
Susumu YOSHIDA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1977/12/25
Vol. E60-E  No. 12  pp. 715-722
Type of Manuscript:  PAPER
Category: Communication Theory
Keyword: 
 Summary | Full Text:PDF(648.3KB)

On the Relation between an Encoding Automaton and the Power Spectrum of Its Output Sequence
Susumu YOSHIDA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1976/05/25
Vol. E59-E  No. 5  pp. 1-7
Type of Manuscript:  PAPER
Category: Information Theory
Keyword: 
 Summary | Full Text:PDF(497.6KB)