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Shunsuke OKUMURA

Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM Jinwook JUNG Yohei NAKATA Shunsuke OKUMURA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 528-537 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: low-voltage adaptive cache design, reconfiguring associativity, dynamic voltage frequency scaling, 7T/14T SRAM,
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A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells Shunsuke OKUMURA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2226-2233 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: SRAM, chip ID, physical unclonable function (PUF),
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Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/10/01 Vol. E95-C No. 10 pp. 1675-1681 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SRAM, soft error, multiple-bit upset (MBU), single-event upset (SEU), error correction coding (ECC), alpha particle, neutron particle,
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Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Koji NII Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 pp. 1359-1365 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: SRAM, single-event upset (SEU), bit error rate (BER), soft error rate (SER), neutron particle, alpha particle,
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A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke YOSHIMOTO Masaharu TERADA Shunsuke OKUMURA Toshikazu SUZUKI Shinji MIYANO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 572-578 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, 8T, low energy, disturb, half select, write back,
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A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme Shunsuke OKUMURA Hidehiro FUJIWARA Kosuke YAMAGUCHI Shusuke YOSHIMOTO Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 579-585 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, FD-SOI, Inter-die variation,
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7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory Shunsuke OKUMURA Yuki KAGIYAMA Yohei NAKATA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2693-2700 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: SRAM DMA, transactional memory, checkpoint and recovery, multi-core processor,
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A Dependable SRAM with 7T/14T Memory Cells Hidehiro FUJIWARA Shunsuke OKUMURA Yusuke IGUCHI Hiroki NOGUCHI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 423-432 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: SRAM, dependability, quality of a bit,
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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing Hiroki NOGUCHI Yusuke IGUCHI Hidehiro FUJIWARA Shunsuke OKUMURA Yasuhiro MORITA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 543-552 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: 8T SRAM cell, 10T SRAM cell, low-power SRAM, non-precharge SRAM, two-port SRAM, video processing,
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