Shunichi KAERIYAMA


A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests
Shunichi KAERIYAMA Mikihiro KAJITA Masayuki MIZUNO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1  pp. 102-109
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock generatorduty ratiofrequency synthesisI/Q balancejittertiming margin
 Summary | Full Text:PDF(2.3MB)

Solid-Electrolyte Nanometer Switch
Naoki BANNO Toshitsugu SAKAMOTO Noriyuki IGUCHI Hisao KAWAURA Shunichi KAERIYAMA Masayuki MIZUNO Kozuya TERABE Tsuyoshi HASEGAWA Masakazu AONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1492-1498
Type of Manuscript:  INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
solid-electrolyteelectrochemical reactionion diffusionprogrammable logic
 Summary | Full Text:PDF(1MB)