Shuichi SAKAI


Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 822-837
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorregister filemultibanking
 Summary | Full Text:PDF(3.2MB)

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 232-244
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
register fileregister cachedigital designfreePDK
 Summary | Full Text:PDF(3.2MB)

An Inductive Method to Select Simulation Points
MinSeong CHOI Takashi FUKUDA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2891-2900
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
simulation pointsampling simulationmicroarchitectureprocessor architecturesimulationcomputer architecture
 Summary | Full Text:PDF(2.6MB)

Address Order Violation Detection with Parallel Counting Bloom Filters
Naruki KURATA Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 580-593
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
processor architectureload-store queuebloom filterlow-energy technologies
 Summary | Full Text:PDF(1.8MB)

Register Indirect Jump Target Forwarding
Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2  pp. 278-288
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architectureregister indirect jumpobject-oriented programming
 Summary | Full Text:PDF(1.7MB)

Low-Overhead Architecture for Security Tag
Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 69-78
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecturetagged architectureinformation securityinformation flow tracking
 Summary | Full Text:PDF(507.1KB)

Ultra Dependable Processor
Shuichi SAKAI Masahiro GOSHIMA Hidetsugu IRIE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1386-1393
Type of Manuscript:  INVITED PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
microprocessor architecturedependable computingattacksfaultserrorsfailuressoft errorstiming errorstamper resistanceinformation flowinjection attackdependability manager
 Summary | Full Text:PDF(1.1MB)

Processor Pipeline Design for Fast Network Message Handling in RWC-1 Multiprocessor
Hiroshi MATSUOKA Kazuaki OKAMOTO Hideo HIRONO Mitsuhisa SATO Takashi YOKOTA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1391-1397
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
massively parallel computerloosely coupled multiprocessormulti-threaded executionsuper-scalar processorprocessor pipeline
 Summary | Full Text:PDF(652.9KB)

hMDCE: The Hierarchical Multidimensional Directed Cycles Ensemble Network
Takashi YOKOTA Hiroshi MATSUOKA Kazuaki OKAMOTO Hideo HIRONO Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1099-1106
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
interconnection networkshierarchical networksrouting algorithmsperformance evaluationmassively parallel computersmultithreaded architecture
 Summary | Full Text:PDF(704KB)

Message-Based Efficient Remote Memory Access on a Highly Parallel Computer EM-X
Yuetsu KODAMA Hirohumi SAKANE Mitsuhisa SATO Hayato YAMANA Shuichi SAKAI Yoshinori YAMAGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1065-1071
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Architectures
Keyword: 
Fine grain communicationmultithread architecturedistributed shared memory
 Summary | Full Text:PDF(723.5KB)

Synchronization Mechanisms of a Highly Parallel Dataflow Machine EM-4
Yoshinori YAMAGUCHI Shuichi SAKAI Yuetsu KODAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/01/25
Vol. E74-D  No. 1  pp. 204-213
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
 Summary | Full Text:PDF(882.8KB)