Shoto TAMAI


Proposal of Stacked Type Fe-FET NOR/NOR Array and Its Application to Combinational Logic
Shoto TAMAI Takumi SATO Shigeyoshi WATANABE 
Publication:   C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2016/11/01
Vol. J99-C  No. 11  pp. 550-563
Type of Manuscript:  PAPER
Category: 
Keyword: 
NOR type memoryFe-FETvertical transistorNOR arraylogic LSIreconfigurable architecturehigh speed operation
 Summary | Full Text(in Japanese):PDF(1.6MB)

Proposal of Stacked Type Memory/Logic Circuit Array and Its Application to LUT (Look Up Table)
Shoto TAMAI Takumi SATO Shigeyoshi WATANABE 
Publication:   C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2016/07/01
Vol. J99-C  No. 7  pp. 347-356
Type of Manuscript:  PAPER
Category: 
Keyword: 
NAND type memoryBiCS technologyFe-FETstacked structureLUTFPGAlogic LSIreconfigurable architecture
 Summary | Full Text(in Japanese):PDF(1.3MB)

Study for Reading Method of Stacked NAND Type MRAM Using Spin Transistor
Shoto TAMAI Shigeyoshi WATANABE 
Publication:   C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2008/11/01
Vol. J91-C  No. 11  pp. 666-667
Type of Manuscript:  LETTER
Category: 
Keyword: 
non-volatile memoryMRAMspin transistorstacked NAND structure
 Summary | Full Text(in Japanese):PDF(144.4KB)