Shoichiro YAMADA


An Optimal Block Terminal Assignment Algorithm for VLSI Data Path Allocation
Shoichiro YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 564-566
Type of Manuscript:  Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
block terminal assignmentdata path allocationhigh-level synthesisinteger linear programming
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A Mathematical Formulation of Allocation and Floorplanning Problem in VLSI Data Path Synthesis
Shoichiro YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 1043-1049
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
high-level synthesisdata path allocationfloorplanningmixed integer linear programming
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Wire Length Expressions for Analytical Placement Approach
Shoichiro YAMADA Masahiro KASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4  pp. 716-718
Type of Manuscript:  LETTER
Category: Computer Aided Design (CAD)
Keyword: 
placementCADVLSI design
 Summary | Full Text:PDF(180.1KB)

An Efficient Algorithm for Multiple Folded Gate Matrix Layout
Shoichiro YAMADA Shunichi NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1645-1651
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
gate matrix layoutfoldingmodule generatormulti-way mini-cutpolar graph
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A Fuzzy-Theoretic Timing Driven Placement Method
Ze Cang GU Shoichiro YAMADA Kunio FUKUNAGA Shojiro YONEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1280-1285
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
fuzzyblock placementpath delaytiming driven placement
 Summary | Full Text:PDF(514.5KB)

Timing Driven Placement Based on Fuzzy Theory
Ze Cang GU Shoichiro YAMADA Shojiro YONEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 917-919
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Spring Conference)
Category: 
Keyword: 
fuzzytimingplacementVLSI
 Summary | Full Text:PDF(159KB)

A Fuzzy-Theoretic Block Placement Algorithm for VLSI Design
Z. C. GU Shoichiro YAMADA Shojiro YONEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/25
Vol. E74-A  No. 10  pp. 3065-3071
Type of Manuscript:  Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology
Keyword: 
 Summary | Full Text:PDF(421.1KB)

Dynamic Compaction Considering Routing Region for Building-Block Layout
Shoichiro YAMADA Hirohisa TANABE Tamotsu KASAI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1374-1381
Type of Manuscript:  Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology
Keyword: 
 Summary | Full Text:PDF(565.9KB)