Shinobu NAGAYAMA


A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1583-1591
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
index generation functionslinear decompositionincompletely specified functionsbalanced decision treecontent-addressable memorylogic designheuristic
 Summary | Full Text:PDF(694.2KB)

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER Mitchell A. THORNTON Theodore W. MANIKAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2234-2242
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
minimization algorithm of the number of edgesEVMDDsgrouping variables for optimization of decision diagramsmulti-state systemssystem analysis using decision diagrams
 Summary | Full Text:PDF(891.9KB)

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2059-2067
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
two-variable numeric function generators (NFGs)edge-valued multiple-valued decision diagrams (EVMDDs)edge-valued binary decision diagrams (EVBDDs)graph-based representation of numeric functionsprogrammable memory-based architecture
 Summary | Full Text:PDF(391KB)

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2752-2761
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
edge-valued binary decision diagrams (EVBDDs)recursive segmentationpiecewise polynomial approximationnumerical function generators (NFGs)programmable architecture
 Summary | Full Text:PDF(411KB)

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3510-3518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
LUT cascades2nd-order Chebyshev approximationnon-uniform segmentationNFGsautomatic synthesisFPGA
 Summary | Full Text:PDF(308KB)

A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
LUT cascadeLUT ringmultiple-output functionreconfigurable logicprogrammable logic device
 Summary | Full Text:PDF(675.1KB)

Area-Time Complexities of Multi-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Yukihiro IGUCHI Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A  No. 5  pp. 1020-1028
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
decision diagramsthe number of nodesarea-time complexityrandomly generated functionrepresentation of logic functions
 Summary | Full Text:PDF(307.2KB)

Compact Representations of Logic Functions Using Heterogeneous MDDs
Shinobu NAGAYAMA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3168-3175
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
heterogeneous MDDROBDDFBDDAPLmemory size
 Summary | Full Text:PDF(192.4KB)