Shinji KIMURA


Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System
Li GUO Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   
Publication Date: 2017/11/01
Vol. E100-A  No. 11  pp. 2416-2424
Type of Manuscript:  PAPER
Category: Coding Theory
Keyword: 
lossy embedded compressionmemory-traffic-to-distortion optimizationdistortion controlframe-levelfixed data reduction ratio
 Summary | Full Text:PDF(3MB)

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 223-231
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
3D IC designmotion estimation processorhamburger architecturememory stacking
 Summary | Full Text:PDF(1.6MB)

Accelerating HEVC Inter Prediction with Improved Merge Mode Handling
Zhengxue CHENG Heming SUN Dajiang ZHOU Shinji KIMURA 
Publication:   
Publication Date: 2017/02/01
Vol. E100-A  No. 2  pp. 546-554
Type of Manuscript:  Special Section PAPER (Special Section on Image Media Quality)
Category: VIDEO CODING
Keyword: 
HEVC/H.265merge modeinter predictionencoding
 Summary | Full Text:PDF(2.4MB)

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform
Heming SUN Dajiang ZHOU Shuping ZHANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2375-2387
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
HEVCde-quantizationinverse transformlow-powerlow-costvideo coding
 Summary | Full Text:PDF(3MB)

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory
Masashi TAWADA Shinji KIMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2494-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
non-volatile memorybit-write reductionenergy reductionwrite-reduction codeerror-correcting code
 Summary | Full Text:PDF(1.5MB)

Low-Power Motion Estimation Processor with 3D Stacked Memory
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1431-1441
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
3DIC designmotion estimation processorlow power designmemory stacking
 Summary | Full Text:PDF(4.1MB)

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding
Jiayi ZHU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2488-2497
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high efficiency video codingsample adaptive offsetRate Distortion Optimization (RDO) VLSI architecture
 Summary | Full Text:PDF(4.1MB)

An Exact Approach for GPC-Based Compressor Tree Synthesis
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2553-2560
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
compressor treegeneralized parallel counterinteger linear programmingarithmetic synthesis
 Summary | Full Text:PDF(850.4KB)

Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization
Yu JIN Zhe DU Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2568-2575
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
pseudo power gatinglow power combinational circuitgate level power optimization
 Summary | Full Text:PDF(1.8MB)

Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
Naoya OKADA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6  pp. 1264-1272
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
write control methodnonvolatile flip-flopstate transition analysisclock gating
 Summary | Full Text:PDF(1.7MB)

On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
Yu JIN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2191-2198
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dynamic power reductionswitching activity reductioncontrolling value-based power controllingBDD
 Summary | Full Text:PDF(1.8MB)

Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1347-1358
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
actual power reductionautomatic multi-stage clock gating optimizationILP formulationswitching activityBDDMIP optimizer
 Summary | Full Text:PDF(2.8MB)

Multi-Operand Adder Synthesis Targeting FPGAs
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2579-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
multi-operand addergeneralized parallel counterarithmetic synthesisFPGA
 Summary | Full Text:PDF(718KB)

Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2472-2480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
automatic clock gating generationlow powerdynamic power reductionBDD
 Summary | Full Text:PDF(1.3MB)

FOREWORD
Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 2961-2961
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(54.2KB)

Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity
Lei CHEN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3111-3118
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
power gatingmulti-threshold CMOS (MTCMOS)controlling valuedynamic power reductionmaximum depth constraintCV-based power gating
 Summary | Full Text:PDF(562.5KB)

Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping
Chengjie ZANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6  pp. 1454-1463
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SystemVerilog Assertionassertion checkerfinite input-memory automaton
 Summary | Full Text:PDF(261.6KB)

Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration
Yun YANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3431-3442
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
power/ground (P/G) networkgenetic algorithm (GA)gene disturbancetrapezoidal modified Euler (TME)hybrid-SLPglobal area optimizationdynamic signal simulation
 Summary | Full Text:PDF(989.3KB)

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3531-3538
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
power gatingmulti-threshold CMOS (MTCMOS) technologyBDDcontrolling valueleakage power reduction
 Summary | Full Text:PDF(767KB)

The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
Yun YANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1101-1111
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
jumping systolic array (JSA)processing element (PE)matrix multiplicationfully concurrent operationfast process speed
 Summary | Full Text:PDF(1MB)

Issue Mechanism for Embedded Simultaneous Multithreading Processor
Chengjie ZANG Shigeki IMAI Steven FRANK Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4  pp. 1092-1100
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
simultaneous multithreadingparallel flagbalance round-robin policy
 Summary | Full Text:PDF(836.4KB)

Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification
Xingwen XU Shinji KIMURA Kazunari HORIKAWA Takehiko TSUCHIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3451-3457
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
model checkingtransition coverage
 Summary | Full Text:PDF(414.2KB)

Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3427-3434
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
HDLhigh-level synthesisbit-length optimizationnon-linear programming
 Summary | Full Text:PDF(315KB)

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains
Youhua SHI Nozomu TOGAWA Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4  pp. 996-1004
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
test data compressiontest channelsscan test
 Summary | Full Text:PDF(445.2KB)

FOREWORD
Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3273-3273
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(39.7KB)

A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs
Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3193-3199
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test data compressiontest slicemultiple scan chainATE
 Summary | Full Text:PDF(738.1KB)

A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction
Youhua SHI Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3208-3215
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test data compressionscan chain reconfigurationrun-length codingscan-in power consumption
 Summary | Full Text:PDF(465.2KB)

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3056-3062
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
reseedingLFSRBISTtest pattern generation
 Summary | Full Text:PDF(1MB)

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3184-3191
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
HDLhigh-level synthesisparallelizing compilerbit length
 Summary | Full Text:PDF(863.4KB)

Look Up Table Compaction Based on Folding of Logic Functions
Shinji KIMURA Atsushi ISHII Takashi HORIYAMA Masaki NAKANISHI Hirotsugu KAJIHARA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2701-2707
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
field programmable gate array (FPGA)LUT architecturereconfigurable logic
 Summary | Full Text:PDF(329.8KB)

Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion
Kazuhiro NAKAMURA Shinji MARUOKA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2600-2607
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
timing verificationmaximum delay analysismulti-cycle pathspropositional satisfiability
 Summary | Full Text:PDF(365KB)

Robust Heuristics for Multi-Level Logic Simplification Considering Local Circuit Structure
Qiang ZHU Yusuke MATSUNAGA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2520-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
multi-level logic simplificationsatisfiability don't caresobservability don't caresadaptive subnetwork
 Summary | Full Text:PDF(325.8KB)

Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization
Kazuyoshi TAKAGI Hiroshi HATAKEDA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2407-2413
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Free BDDPass-Transistor LogicBoolean functionlogic minimization
 Summary | Full Text:PDF(680.1KB)

Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2338-2346
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesishardware/software codesignVHDLC languagecompiler
 Summary | Full Text:PDF(724.5KB)

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2515-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
timing verificationmaximum delay analysismultiple clock operationfalse path
 Summary | Full Text:PDF(546.5KB)

Prciseness of Discrete Time Verification
Shinji KIMURA Shunsuke TSUBOTA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1755-1759
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
timing verificationdiscrete time analysistiming simulationunit time selection
 Summary | Full Text:PDF(390.9KB)

Timing Verification of Logic Circuits with Combined Delay Model
Shinji KIMURA Shigemi KASHIMA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1230-1238
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
timing verificationcomputer aided designlogic simulation
 Summary | Full Text:PDF(741.8KB)

Parallel Binary Decision Diagram Manipulation
Shinji KIMURA Tsutomu IGAKI Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1255-1262
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagramparallel algorithmlogic verification
 Summary | Full Text:PDF(678.3KB)

The Least-Fixed-Point of Feedback-Loops of Logic Circuits for a Set of Input Strings
Shinji KIMURA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E  No. 12  pp. 1344-1349
Type of Manuscript:  Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology
Keyword: 
 Summary | Full Text:PDF(502.1KB)