Shin-ichi MINATO


Verifying Scenarios of Proximity-Based Federations among Smart Objects through Model Checking and Its Advantages
Reona MINODA Shin-ichi MINATO 
Publication:   
Publication Date: 2017/06/01
Vol. E100-D  No. 6  pp. 1172-1181
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Formal techniques
Keyword: 
ubiquitous computingcatalytic reaction networkformal verificationmodel checkingsmart object
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Implicit Generation of Pattern-Avoiding Permutations by Using Permutation Decision Diagrams
Yuma INOUE Takahisa TODA Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/06/01
Vol. E97-A  No. 6  pp. 1171-1179
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
pattern-avoiding permutationsgenerating algorithmsdecision diagramsπDDexperimental algorithms
 Summary | Full Text:PDF(1.3MB)

Techniques of BDD/ZDD: Brief History and Recent Activity
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7  pp. 1419-1429
Type of Manuscript:  INVITED SURVEY PAPER
Category: 
Keyword: 
BDDZDDdecision diagramdiscrete structurealgorithmdata structure
 Summary | Full Text:PDF(1.2MB)

On Tackling Flash Crowds with URL Shorteners and Examining User Behavior after Great East Japan Earthquake
Takeru INOUE Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/07/01
Vol. E95-B  No. 7  pp. 2210-2221
Type of Manuscript:  Special Section PAPER (Special Section on Future Internet Technologies against Present Crises)
Category: 
Keyword: 
flash crowdURL shortenerCDNdisasterGreat East Japan Earthquake
 Summary | Full Text:PDF(2.2MB)

A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions
Yusaku KANETA Shingo YOSHIZAWA Shin-ichi MINATO Hiroki ARIMURA Yoshikazu MIYANAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/07/01
Vol. E95-D  No. 7  pp. 1847-1857
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGAstring matchingregular expression matchingbit-parallel algorithmevent stream processing
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DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3793-3802
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
quantum circuitverificationdecision diagram
 Summary | Full Text:PDF(483.7KB)

Manipulation of Large-Scale Polynomials Using BMDs
Dror ROTTER Kiyoharu HAMAGUCHI Shin-ichi MINATO Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1774-1781
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
zero-suppressed binary decision diagrams (BDD)binary moment diagramspolynomials
 Summary | Full Text:PDF(554.8KB)

BEM-: An Arithmetic Boolean Expression Manipulator Using BDDs
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1721-1729
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
BDD (binary decision diagram)Boolean functionarithmetic Boolean expressionB-to-(Boolean-to-integer) functioncombinatorial problem
 Summary | Full Text:PDF(730.2KB)

Fast Generation of Prime-Irredundant Covers from Binary Decision Diagrams
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6  pp. 967-973
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
BDDs (Binary Decision Diagrams)prime-irredundant coversBoolean functionssum-of-products formslogic synthesis
 Summary | Full Text:PDF(531.1KB)

Minimum-Width Method of Variable Ordering for Binary Decision Diagrams
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 392-399
Type of Manuscript:  Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagramsboolean functionlogic synthesisvariable ordering
 Summary | Full Text:PDF(616.5KB)