Shigeyoshi WATANABE


Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1051-1058
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuitambipolar double-gate devicesdynamic logicCNTFETs
 Summary | Full Text:PDF(817.2KB)

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs
Hiroshi NINOMIYA Manabu KOBAYASHI Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 675-678
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
reconfigurable logic circuit designambipolar devicedouble-gate CNTFETbinary decision diagramarithmetic logic unit
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Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1642-1644
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuitambipolar double-gate devicesdynamic logicCNTFETs
 Summary | Full Text:PDF(244.8KB)

Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram
Hiroshi NINOMIYA Manabu KOBAYASHI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1  pp. 356-359
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic designambipolar devicedouble gate CNTFETbinary decision diagram
 Summary | Full Text:PDF(615.3KB)

FOREWORD
Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 533-533
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(141.9KB)

Study of LOCOS-Induced Anomalous Leakage Current in Thin Film SOI MOSFET's
Shigeru KAWANAKA Shinji ONGA Takako OKADA Michihiro OOSE Toshihiko IINUMA Tomoaki SHINO Takashi YAMADA Makoto YOSHIMI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7  pp. 1341-1346
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
SOILOCOS isolationcrystal defectleakage currentstress
 Summary | Full Text:PDF(2.3MB)

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
 Summary | Full Text:PDF(803.3KB)

An Ultra Low Voltage SOI CMOS Pass-Gate Logic
Tsuneaki FUSE Yukihito OOWAKI Mamoru TERAUCHI Shigeyoshi WATANABE Makoto YOSHIMI Kazunori OHUCHI Jun'ichi MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 472-477
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOI0.5 V operationultra low voltagepass-gate logicbody-bias control
 Summary | Full Text:PDF(545.6KB)

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMpower dissipationreliabilitybit-linewordlinesmall swingthreshold voltagesense amplifiermemory cell
 Summary | Full Text:PDF(772.8KB)

New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
Yukihito OOWAKI Keiji MABUCHI Shigeyoshi WATANABE Kazunori OHUCHI Jun'ichi MATSUNAGA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 845-851
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
α-particlesoft errorDRAM
 Summary | Full Text:PDF(605.2KB)

Simulation Model of Self Adaptive Behavior in Quasi-Ecosystem
Tomomi TAKASHINA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/05/25
Vol. E78-A  No. 5  pp. 573-576
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Fall Conference)
Category: 
Keyword: 
quasi-ecosystemartificial lifeautonomous agentself adaptive behavior
 Summary | Full Text:PDF(276.8KB)

Measuring the Student Knowledge State in Concept Learning: An Approximate Student Model
Enrique Gonzalez TORRES Takeshi IIDA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/10/25
Vol. E77-D  No. 10  pp. 1170-1178
Type of Manuscript:  PAPER
Category: Artificial Intelligence and Cognitive Science
Keyword: 
student modelfuzzy inferenceconcept learnignskill acquisitionlearning environment
 Summary | Full Text:PDF(862.2KB)

Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's
Daisaburo TAKASHIMA Shigeyoshi WATANABE Hiroaki NAKANO Yukihito OOWAKI Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 869-872
Type of Manuscript:  Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(369.1KB)

Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory
Daisaburo TAKASHIMA Shigeyoshi WATANABE Hiroaki NAKANO Yukihito OOWAKI Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 771-777
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(544.7KB)

Estimation of Yield Suppression for 1.5 V-1 Gbit DRAMs Caused by Threshold Voltage Variation of MOSFET due to Microscopic Fluctuation in Dopant Distributions
Shigeyoshi WATANABE Takaaki MINAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 273-279
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
1 Gbit DRAM1.5 Vyieldthreshold voltage variationredundancy
 Summary | Full Text:PDF(563.6KB)

A Parallel Scheduling of Multi-Step Diakoptics for Three Dimensional Finite Differece Method
Kazuhiro MOTEGI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1822-1829
Type of Manuscript:  PAPER
Category: Numerical Analysis and Self-Validation
Keyword: 
parallel schedulingparallel direct solution methodfinite difference method
 Summary | Full Text:PDF(666.3KB)

Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's
Daisaburo TAKASHIMA Shigeyoshi WATANABE Tsuneaki FUSE Kazumasa SUNOUCHI Takahiko HARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 844-849
Type of Manuscript:  Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
 Summary | Full Text:PDF(763KB)

A Parallel Algorithm for Solving Two Dimensional Device Simulation by Direct Solution Method and Its Evaluation on the AP 1000
Kazuhiro MOTEGI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7  pp. 920-922
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Spring Conference)
Category: 
Keyword: 
parallel schedulingparallel direct solution methoddevice simulation
 Summary | Full Text:PDF(200KB)

Word-Line Architecture for Highly Reliable 64-Mb DRAM
Daisaburo TAKASHIMA Yukihito OOWAKI Ryu OGIWARA Yohji WATANABE Kenji TSUCHIDA Masako OHTA Hiroaki NAKANO Shigeyoshi WATANABE Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 501-507
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF(680.9KB)

A Parallel Computation Method in Device Simulation
Kazuhiro MOTEGI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1792-1795
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Nonlinear Problems and Simulation
Keyword: 
 Summary | Full Text:PDF(310KB)

Script-Based Monitor for Mixed-Initiative Intelligent Tutoring Systems
Shigeyoshi WATANABE Hiromi OIKE Jyuichi MIYAMICHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/03/25
Vol. E73-E  No. 3  pp. 315-322
Type of Manuscript:  Special Section PAPER (Special Issue on Intelligent Computer Systems for Education)
Category: 
Keyword: 
 Summary | Full Text:PDF(640.9KB)

A New Memory Cell Array Structure for High Density DRAMs
Tatsuo IKAWA Tsuneaki FUSE Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/04/25
Vol. E69-E  No. 4  pp. 272-273
Type of Manuscript:  Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Silicon Devices and Integrated Circuits
Keyword: 
 Summary | Full Text:PDF(129.5KB)