IEICE SEARCH SYSTEM

Shigetaka KUMASHIRO

On-Chip In-Place Measurements of V_th and Signal/Substrate Response of Differential Pair Transistors Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/01/01 Vol. E95-C No. 1 pp. 137-145 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: on-chip monitor, substrate noise, differential amplifier,
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On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement Masaaki SODA Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1024-1031 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: noise, sine wave, harmonic,
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A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits Yoji BANDO Satoshi TAKAYA Toru OHKAWA Toshiharu TAKARAMOTO Toshio YAMADA Masaaki SOUDA Shigetaka KUMASHIRO Tohru MOGAMI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 495-503 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: on-chip monitor, power supply noise,
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Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/08/01 Vol. E93-C No. 8 pp. 1349-1358 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: STI, stress, model, verification, enhancement,
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Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress Kenta YAMADA Takashi SATO Shuhei AMAKAWA Noriaki NAKAYAMA Kazuya MASU Shigetaka KUMASHIRO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/07/01 Vol. E91-C No. 7 pp. 1142-1150 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: STI, stress, modeling, SPICE, layout-aware,
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A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential Dondee NAVARRO Takeshi MIZOGUCHI Masami SUETAKE Kazuya HISAMITSU Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/05/01 Vol. E88-C No. 5 pp. 1079-1086 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: pinch-off region, channel-length modulation, overlap capacitance, surface-potential-based modeling, circuit simulation,
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1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation Shizunori MATSUMOTO Hiroaki UENO Satoshi HOSOKAWA Toshihiko KITAMURA Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Tatsuya OHGURO Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/02/01 Vol. E88-C No. 2 pp. 247-254 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: 100 nm-MOSFET, 1/f noise, measurement, modeling,
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Circuit-Simulation Model of C_gd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients Dondee NAVARRO Hiroaki KAWANO Kazuya HISAMITSU Takatoshi YAMAOKA Masayasu TANAKA Hiroaki UENO Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/03/01 Vol. E86-C No. 3 pp. 474-480 Type of Manuscript: INVITED PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02)) Category: Keyword: gate-drain capacitance, surface-potential based modeling, lateral field gradient, pocket-implant technology,
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Circuit Simulation Models for Coming MOSFET Generations Mitiko MIURA-MATTAUSCH Hiroaki UENO Hans Juergen MATTAUSCH Shigetaka KUMASHIRO Tetsuya YAMAGUCHI Kyoji YAMASHITA Noriaki NAKAYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 740-748 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: MOSFET model, surface potential, charge based modeling, sub-100 nm technology,
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Advanced Process/Device Modeling and Its Impact on the CMOS Design Solution Shigetaka KUMASHIRO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/08/20 Vol. E83-C No. 8 pp. 1281-1287 Type of Manuscript: INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99)) Category: Simulation Methodology and Environment Keyword: process modeling, device modeling, 0.13 [µm] CMOS,
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Modeling of Channel Boron Distribution in Deep Sub-0.1 µm n-MOSFETs Shigetaka KUMASHIRO Hironori SAKAMOTO Kiyoshi TAKEUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/20 Vol. E82-C No. 6 pp. 813-820 Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: deep sub-0.1 [µm] n-MOSFET, reverse short channel effect, point-defect pair diffusion model, inverse modeling,
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Efficient Transient Device Simulation with AWE Macromodels and Domain Decomposition Howard C. READ Shigetaka KUMASHIRO Andrzej STROJWAS
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/02/20 Vol. E77-C No. 2 pp. 236-247 Type of Manuscript: Special Section PAPER (Special Issue on 1993 VLSI Process and Device Modeling Workshop (VPAD 93)) Category: Numerics Keyword: semiconductor materials and devices,
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