Shigeru YAMASHITA


A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips
Trung Anh DINH Shigeru YAMASHITA Tsung-Yi HO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/02/01
Vol. E99-A  No. 2  pp. 570-578
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
digital microfluidic biochipscombinational logicpin-count reductiongeneral purpose
 Summary | Full Text:PDF(1.4MB)

An Energy-Efficient Patchable Accelerator and Its Design Methods
Hiroaki YOSHIDA Masayuki WAKIZAKA Shigeru YAMASHITA Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2507-2517
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
engineering changehigh-level synthesisenergy efficiency
 Summary | Full Text:PDF(1.9MB)

Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips
Trung Anh DINH Shigeru YAMASHITA Tsung-Yi HO Yuko HARA-AZUMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2668-2679
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
flow-based microfluidic biochiparchitectural synthesisbindingschedulingclique
 Summary | Full Text:PDF(2MB)

Selective Check of Data-Path for Effective Fault Tolerance
Tanvir AHMED Jun YAO Yuko HARA-AZUMI Shigeru YAMASHITA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1592-1601
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
low powerfault-tolerant computingFU array
 Summary | Full Text:PDF(903.6KB)

Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication
Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/01/01
Vol. E96-D  No. 1  pp. 1-8
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
multiparty communication complexityquantum computationquantum nondeterminismtensor rank
 Summary | Full Text:PDF(285.4KB)

Quantum Walks on the Line with Phase Parameters
Marcos VILLAGRA Masaki NAKANISHI Shigeru YAMASHITA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/03/01
Vol. E95-D  No. 3  pp. 722-730
Type of Manuscript:  Special Section PAPER (Special Section on Foundations of Computer Science – Mathematical Foundations and Applications of Computer Science and Algorithms –)
Category: 
Keyword: 
quantum computationrandom walksquantum walksasymptotic approximation
 Summary | Full Text:PDF(289.9KB)

Multi-Party Quantum Communication Complexity with Routed Messages
Seiichiro TANI Masaki NAKANISHI Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2  pp. 191-199
Type of Manuscript:  Special Section PAPER (Special Section on Foundations of Computer Science)
Category: 
Keyword: 
quantum communication complexitynetwork topologydistributed computing
 Summary | Full Text:PDF(436.3KB)

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3793-3802
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
quantum circuitverificationdecision diagram
 Summary | Full Text:PDF(483.7KB)

Robust Quantum Algorithms Computing OR with ε-Biased Oracles
Tomoya SUZUKI Shigeru YAMASHITA Masaki NAKANISHI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/02/01
Vol. E90-D  No. 2  pp. 395-402
Type of Manuscript:  Special Section PAPER (Special Section on Foundations of Computer Science)
Category: Quantum Computing
Keyword: 
quantum computingbiased oraclephase estimation
 Summary | Full Text:PDF(245.7KB)

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs
Mitsuru TOMONO Masaki NAKANISHI Shigeru YAMASHITA Kazuo NAKAJIMA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3416-3426
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
algorithmonline placementpartially reconfigurable FPGAsreconfigurable computing
 Summary | Full Text:PDF(948KB)

SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits
Katsunori TANAKA Shigeru YAMASHITA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 1038-1046
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic designset of pairs of functions to be distinguished (SPFD)look-up-table-based (LUT-based) field programmable gate array (FPGA)SPFD-based effective wire addition
 Summary | Full Text:PDF(265.4KB)

Quantum Sampling for Balanced Allocations
Kazuo IWAMA Akinori KAWACHI Shigeru YAMASHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/01/01
Vol. E88-D  No. 1  pp. 39-46
Type of Manuscript:  Special Section PAPER (Special Section on Foundations of Computer Science)
Category: 
Keyword: 
quantum computingload balancingballs-and-bins game
 Summary | Full Text:PDF(207.2KB)

A General Framework to Use Various Decomposition Methods for LUT Network Synthesis
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2915-2922
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
functional decompositionalgebraic decompositionfield programmable gate array (FPGA)look-up table (LUT)
 Summary | Full Text:PDF(363.4KB)

Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications
Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2513-2519
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
multi-level logic synthesissum-of-products expressionimplicit cube set representationkernel
 Summary | Full Text:PDF(345.5KB)

Restructuring Logic Representations with Simple Disjunctive Decompositions
Hiroshi SAWADA Shigeru YAMASHITA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2538-2544
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
simple disjunctive decompositionsymmetric variables ordered binary decision diagrammulti-level logic circuit
 Summary | Full Text:PDF(635.6KB)

Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2554-2562
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic optimizationFPGAsSPFDsPSPFDs
 Summary | Full Text:PDF(818.2KB)

An Efficient Method for Finding an Optimal Bi-Decomposition
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2529-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decompositionbi-decompositionANDXORlook-up table
 Summary | Full Text:PDF(755.8KB)