Seong Yong OHM


An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappinglogic minimizationBoolean networkfield-programmable gate array
 Summary | Full Text:PDF(534.1KB)

An Optimal Scheduling Approach Using Lower Bound in High-Level Synthesis
Seong Yong OHM Fadi J. KURDAHI Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 231-236
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high-level synthesisschedulinglower bound estimation
 Summary | Full Text:PDF(579.4KB)