Author List
Japanese Page
SITE TOP
Login
To browse Full-Text PDF.
>
Forgotten your password?
Menu
Search
Full-Text Search
Search(JPN)
Latest Issue
A Fundamentals
Trans.Fundamentals.
JPN Edition(in Japanese)
B Communications
Trans.Commun.
JPN Edition(in Japanese)
C Electronics
Trans.Electron.
JPN Edition(in Japanese)
D Information & Systems
Trans.Inf.&Syst.
JPN Edition(in Japanese)
Abstracts of JPN Edition
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
Archive
Volume List
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
Transactions (1976-1990)
Volume List [JPN Edition]
A JPN Edition(in Japanese)
B JPN Edition(in Japanese)
C JPN Edition(in Japanese)
D JPN Edition(in Japanese)
Editorial Board & Reviewers
Open Access Papers
Trans. Commun.
Trans. Commun.(JPN Edition)
Link
Subscription
Join IEICE
Library/Nonmember
Pay Per View
A Fundamentals
B Communications
C Electronics
D Information & Systems
For Authors
IEICE Home Page
Citation Index
Privacy Policy
Copyright & Permissions
Copyright (c) by IEICE
Seong Tae JHANG
Throttling Capacity Sharing Using Life Time and Reuse Time Prediction in Private L2 Caches of Chip Multiprocessors
Young-Sik EOM
Jong Wook KWAK
Seong Tae JHANG
Chu Shik JHON
Publication:
IEICE TRANSACTIONS on Information and Systems
Publication Date:
2012/06/01
Vol.
E95-D
No.
6
pp.
1676-1679
Type of Manuscript:
LETTER
Category:
Computer System
Keyword:
Chip Multi-Processors
,
private L2 cache
,
capacity sharing
,
cooperative caching
,
Summary
|
Full Text:PDF
(777.4KB)
