Senling WANG


Scan-Out Power Reduction for Logic BIST
Senling WANG Yasuo SATO Seiji KAJIHARA Kohei MIYASE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 2012-2020
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
low powerBISTmulti-cycle testshift power
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