IEICE SEARCH SYSTEM

Satoshi GOTO

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips Wei ZHONG Song CHEN Bo HUANG Takeshi YOSHIMURA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1174-1184 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: networks on chip (NoC), topology synthesis, floorplanning,
	Summary \| Full Text:PDF (2.4MB)

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC Muchen LI Jinjia ZHOU Dajiang ZHOU Xiao PENG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: HEVC, H.264/AVC, deblocking filter, dual-mode, low power, SHV, HD,
	Summary \| Full Text:PDF (2.7MB)

An Integrated Hole-Filling Algorithm for View Synthesis Wenxin YU Weichen WANG Minghui WANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1306-1314 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: DIBR, virtual view, hole-filling, in-painting,
	Summary \| Full Text:PDF (5.3MB)

Bidirectional Local Template Patterns: An Effective and Discriminative Feature for Pedestrian Detection Jiu XU Ning JIANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1204-1213 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: pedestrian detection, feature extraction, bidirectional local template patterns, support vector machine,
	Summary \| Full Text:PDF (4.3MB)

Joint Feature Based Rain Detection and Removal from Videos Xinwei XUE Xin JIN Chenyuan ZHANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1195-1203 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: rain detection, rain removal, bilateral filtering, DWT (discrete wavelet transform),
	Summary \| Full Text:PDF (6MB)

All-Zero Block-Based Optimization for Quadtree-Structured Prediction and Residual Encoding in High Efficiency Video Coding Guifen TIAN Xin JIN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/04/01 Vol. E96-A No. 4 pp. 769-779 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: HEVC, all-zero block, variable block size, residual encoding,
	Summary \| Full Text:PDF (3.5MB)

Content Adaptive Hierarchical Decision of Variable Coding Block Sizes in High Efficiency Video Coding for High Resolution Videos Guifen TIAN Xin JIN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/04/01 Vol. E96-A No. 4 pp. 780-789 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: video coding, HEVC, content adaptive, variable block sized prediction, sum of absolute quantized residual coefficient,
	Summary \| Full Text:PDF (2.9MB)

Correlated Noise Reduction for Electromagnetic Analysis Hongying LIU Xin JIN Yukiyasu TSUNOO Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/01/01 Vol. E96-A No. 1 pp. 185-195 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: electromagnetic analysis (EMA), power analysis, electromagnetic leakage, correlated noise, singular value decomposition,
	Summary \| Full Text:PDF (2.9MB)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX Xiongxin ZHAO Xiao PENG Zhixiang CHEN Dajiang ZHOU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2384-2391 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: WiMAX, bit-serial, layered scheduling, QC-LDPC,
	Summary \| Full Text:PDF (3MB)

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2208-2219 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: dual-vdd, min-cut, voltage assignment, low power, timing constraints,
	Summary \| Full Text:PDF (1.5MB)

Framework of a Contour Based Depth Map Coding Method Minghui WANG Xun HE Xin JIN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 pp. 1270-1279 Type of Manuscript: Special Section PAPER (Special Section on Image Media Quality) Category: Coding & Processing Keyword: DIBR, depth map, MVC, contour coding,
	Summary \| Full Text:PDF (3MB)

Encoder-Unconstrained User Interactive Partial Decoding Scheme Chen LIU Xin JIN Tianruo ZHANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 pp. 1288-1296 Type of Manuscript: Special Section PAPER (Special Section on Image Media Quality) Category: Coding & Processing Keyword: partial decoding, object of interest, H.264/AVC,
	Summary \| Full Text:PDF (7.8MB)

Pedestrian Detection Using Gradient Local Binary Patterns Ning JIANG Jiu XU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 pp. 1280-1287 Type of Manuscript: Special Section PAPER (Special Section on Image Media Quality) Category: Coding & Processing Keyword: pedestrian detection, feature extraction, local binary pattern, support vector machine, gradient local binary pattern,
	Summary \| Full Text:PDF (3.2MB)

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips Wei ZHONG Takeshi YOSHIMURA Bei YU Song CHEN Sheqin DONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 534-545 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: networks on chip (NoC), placement, synthesis, topology,
	Summary \| Full Text:PDF (2MB)

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2482-2489 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power supply noise, power distribution network, signal integrity, circuit simulation,
	Summary \| Full Text:PDF (710.8KB)

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS Xun HE Xin JIN Minghui WANG Dajiang ZHOU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2609-2618 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: SIMD, cache coherence, NoC, GMACs, multicore processor,
	Summary \| Full Text:PDF (3.6MB)

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip Zhixiang CHEN Xiao PENG Xiongxin ZHAO Leona OKAMURA Dajiang ZHOU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2587-2596 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: WPAN, IEEE802.15.3c, LDPC decoder, high data rate, power-efficient,
	Summary \| Full Text:PDF (1.6MB)

Watermarking for HDR Image Robust to Tone Mapping Xinwei XUE Takao JINNO Xin JIN Masahiro OKUDA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/11/01 Vol. E94-A No. 11 pp. 2334-2341 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Image Processing Keyword: HDR image, watermarking, tone mapping, µ-Law, bilateral filtering,
	Summary \| Full Text:PDF (5.4MB)

Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining Tianruo ZHANG Chen LIU Minghui WANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 401-410 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: H.264 encoding, VLSI architecture, region-of-interest, low power,
	Summary \| Full Text:PDF (3.3MB)

Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder Jinjia ZHOU Dajiang ZHOU Gang HE Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 439-447 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: H.264/AVC, motion compensation, 2-D cache, interpolation, Quad-HD, ultra high definition,
	Summary \| Full Text:PDF (1.1MB)

A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder Gang HE Dajiang ZHOU Jinjia ZHOU Tianruo ZHANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 419-427 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: H.264/AVC, intra prediction, data dependency, hardware architecture,
	Summary \| Full Text:PDF (2.1MB)

Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC Yibo FAN Xiaoyang ZENG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 411-418 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: IME, VBSME, 2-D SAD tree, H.264,
	Summary \| Full Text:PDF (1.6MB)

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 pp. 1082-1090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, power distribution networks, signal integrity, circuit simulation,
	Summary \| Full Text:PDF (640.2KB)

Generic Permutation Network for QC-LDPC Decoder Xiao PENG Xiongxin ZHAO Zhixiang CHEN Fumiaki MAEHARA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2551-2559 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: LDPC decoder, reconfigurable, permutation network, parallelism,
	Summary \| Full Text:PDF (1.2MB)

Accurate Human Detection by Appearance and Motion Shaopeng TANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/10/01 Vol. E93-D No. 10 pp. 2728-2736 Type of Manuscript: Special Section PAPER (Special Section on Data Mining and Statistical Science) Category: Keyword: human detection, multi scale block histogram of template, Graphics process unit,
	Summary \| Full Text:PDF (559.7KB)

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications Jinjia ZHOU Dajiang ZHOU Xun HE Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/08/01 Vol. E93-A No. 8 pp. 1425-1433 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: VLSI Design Technology and CAD Keyword: motion vector derivation, DRAM bandwidth, ultra high resolution, video decoder, H.264/AVC,
	Summary \| Full Text:PDF (911.4KB)

Histogram of Template for Pedestrian Detection Shaopeng TANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/07/01 Vol. E93-D No. 7 pp. 1737-1744 Type of Manuscript: Special Section PAPER (Special Section on Machine Vision and its Applications) Category: Keyword: human detection, histogram of template, SVM,
	Summary \| Full Text:PDF (892.9KB)

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network Xiao PENG Zhixiang CHEN Xiongxin ZHAO Fumiaki MAEHARA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 270-278 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: permutation, banyan network, LDPC decoder, reconfigurable,
	Summary \| Full Text:PDF (705KB)

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder Xianmin CHEN Peilin LIU Dajiang ZHOU Jiayi ZHU Xingguang PAN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 253-260 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: high performance, low bandwidth, motion compensation, multi-standard, 2-D cache,
	Summary \| Full Text:PDF (783.9KB)

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications Dajiang ZHOU Jinjia ZHOU Jiayi ZHU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3203-3210 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: H.264/AVC, parallel, deblocking, ultra high resolution, QFHD,
	Summary \| Full Text:PDF (2.1MB)

Voltage and Level-Shifter Assignment Driven Floorplanning Bei YU Sheqin DONG Song CHEN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 2990-2997 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Desing Keyword: voltage-island, voltage assignment, convex network flow, level shifter assignment, white space redistribution,
	Summary \| Full Text:PDF (512.1KB)

Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application Yiqing HUANG Qin LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/11/01 Vol. E92-A No. 11 pp. 2819-2829 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Video Coding Keyword: reconfigurable architecture, H.264/AVC, SAD tree, VLSI, HDTV,
	Summary \| Full Text:PDF (1.3MB)

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2283-2294 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: application partitioning, CAD algorithm, MPSoC, ASIP, synthesis,
	Summary \| Full Text:PDF (1.6MB)

VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis Yiqing HUANG Qin LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/08/01 Vol. E92-A No. 8 pp. 1986-1999 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: Realization Keyword: H.264/AVC, ME, pixel difference, block overlapping, motion feature,
	Summary \| Full Text:PDF (1.3MB)

An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision Dajiang ZHOU Jinjia ZHOU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/08/01 Vol. E92-A No. 8 pp. 1978-1985 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: Realization Keyword: video coding, motion vector coding, motion vector difference, median prediction, prioritized reference decision,
	Summary \| Full Text:PDF (308.6KB)

Hardware-Oriented Early Detection Algorithms for 44 and 88 All-Zero Blocks in H.264 Qin LIU Yiqing HUANG Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1063-1071 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: all-zero block, early detection, sum of absolute difference, hardware-oriented, H.264,
	Summary \| Full Text:PDF (573.7KB)

An Ultra-Low Bandwidth Design Method for MPEG-2 to H.264/AVC Transcoding Xianghui WEI Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1072-1079 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: H.264, MPEG-2, transcoding, motion estimation, search window reuse,
	Summary \| Full Text:PDF (726.7KB)

High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding Tianruo ZHANG Guifen TIAN Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3630-3637 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: H.264/AVC, intra prediction, fast mode decision algorithm, VLSI architecture,
	Summary \| Full Text:PDF (868.6KB)

A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing Schedule Wen JI Yuta ABE Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3622-3629 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: LDPC, message passing algorithm,
	Summary \| Full Text:PDF (564.5KB)

Standard Deviation and Intra Prediction Mode Based Adaptive Spatial Error Concealment (SEC) in H.264/AVC Jun WANG Lei WANG Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-A No. 10 pp. 2954-2962 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Video Coding Keyword: SEC, adaptive, standard deviation, intra prediction mode,
	Summary \| Full Text:PDF (1.1MB)

Variable Block Size Motion Vector Retrieval Schemes for H.264 Inter Frame Error Concealment Lei WANG Jun WANG Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/10/01 Vol. E91-A No. 10 pp. 2945-2953 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Video Coding Keyword: H.264/AVC, variable block size error concealment, motion vector refinement, directional spatio-temporal boundary matching algorithm,
	Summary \| Full Text:PDF (586.4KB)

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2456-2464 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Electronic Circuits and Systems Keyword: hardware/software partitioning, CAD algorithm, search space smoothing, MPSoC, ASIP,
	Summary \| Full Text:PDF (820.8KB)

Edge Block Detection and Motion Vector Information Based Fast VBSME Algorithm Qin LIU Yiqing HUANG Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 pp. 1935-1943 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: Keyword: motion estimation, aliasing, subsampling, multiple reference frame, search range,
	Summary \| Full Text:PDF (875.3KB)

Content-Aware Fast Motion Estimation for H.264/AVC Zhenyu LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 pp. 1944-1952 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing) Category: Keyword: H.264/AVC, motion estimation, early termination, multiple reference frame, variable block size,
	Summary \| Full Text:PDF (1.3MB)

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/06/01 Vol. E91-A No. 6 pp. 1478-1487 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: custom instruction identification, basic convex pattern (BCP), system-on-a-chip (SoC), application specific instruction-set processor (ASIP),
	Summary \| Full Text:PDF (529.7KB)

A High-Speed Design of Montgomery Multiplier Yibo FAN Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 971-977 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: Montgomery multiplier, high-speed, high-radix, scalable,
	Summary \| Full Text:PDF (1.3MB)

A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems Qin LIU Seiichiro HIRATSUKA Kazunori SHIMIZU Shinsuke USHIKI Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 449-456 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: video surveillance system, motion estimation, ME-MC processor, quadtree, low power consumption,
	Summary \| Full Text:PDF (1MB)

Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm Yibo FAN Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 440-448 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: reconfigurable, VBSME, search range reduction, H.264,
	Summary \| Full Text:PDF (1.9MB)

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1054-1061 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low-density parity-check code, message-passing algorithm, intermediate message compression technique, clock gated shift register for intermediate message,
	Summary \| Full Text:PDF (450.2KB)

Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC Yiqing HUANG Zhenyu LIU Yang SONG Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 987-997 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: H.264/AVC, variable block size motion estimation, hardware architecture,
	Summary \| Full Text:PDF (845.4KB)

Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC Zhenxing CHEN Yang SONG Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1015-1022 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: H.264/AVC, VBSME, ASR, MVD,
	Summary \| Full Text:PDF (1.3MB)

An Irregular Search Window Reuse Scheme for MPEG-2 to H.264 Transcoding Xiang-Hui WEI Shen LI Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/03/01 Vol. E91-A No. 3 pp. 749-755 Type of Manuscript: Special Section PAPER (Special Section on Signal Processing for Audio and Visual Systems and Its Implementations) Category: Image Coding and Video Coding Keyword: MPEG-2 to H.264 transcoding, motion estimation, search window reuse,
	Summary \| Full Text:PDF (496.1KB)

An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard Yibo FAN Jidong WANG Takeshi IKENAGA Yukiyasu TSUNOO Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 12-21 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Symmetric Cryptography Keyword: Unequal Secure Encryption, video encryption, selective encryption, H.264/AVC, AES, LEX,
	Summary \| Full Text:PDF (2.2MB)

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms Qi WANG Kazunori SHIMIZU Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1964-1971 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: VLSI Architecture for Communication/Server Systems Keyword: area and power efficient fully-parallel LDPC decoder, improved simplified min-sum algorithms, power-saved strategy,
	Summary \| Full Text:PDF (515.2KB)

Periodic Spectrum Transmission for Single-Carrier Transmission Frequency-Domain Equalization Fumiaki MAEHARA Satoshi GOTO Fumio TAKAHATA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/06/01 Vol. E90-B No. 6 pp. 1407-1414 Type of Manuscript: PAPER Category: Wireless Communication Technologies Keyword: single-carrier (SC) transmission, frequency-domain equalization (FDE), even-numbered samples, frequency diversity, high-level modulation,
	Summary \| Full Text:PDF (723KB)

Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation Ming SHAO Zhenyu LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 756-763 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: H.264/AVC, FME, computation reusing, lossless, VLSI,
	Summary \| Full Text:PDF (781.3KB)

Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation Yang SONG Zhenyu LIU Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 764-770 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: motion estimation (ME), successive elimination algorithm (SEA), multilevel successive elimination algorithm (MSEA), strict multilevel successive elimination algorithm (SMSEA),
	Summary \| Full Text:PDF (501.3KB)

Fast Methods to Estimate Clock Jitter due to Power Supply Noise Koutaro HACHIYA Takayuki OHSHIMA Hidenari NAKASHIMA Masaaki SODA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 741-747 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: clock jitter, power supply noise, clock distribution network, power distribution network,
	Summary \| Full Text:PDF (500.7KB)

Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations Yang SONG Zhenyu LIU Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 108-117 Type of Manuscript: Special Section PAPER (Special Section on Advanced Image Technology) Category: Keyword: motion estimation (ME), partial distortion sorting (PDS), systolic array architecture,
	Summary \| Full Text:PDF (806.2KB)

Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System Yangxing LIU Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 208-216 Type of Manuscript: Special Section PAPER (Special Section on Advanced Image Technology) Category: Keyword: traffic sign detection, geometrical analysis, physical analysis, text detection,
	Summary \| Full Text:PDF (1.1MB)

Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding Shen LI Lingfeng LI Takeshi IKENAGA Shunichi ISHIWATA Masataka MATSUI Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 pp. 90-98 Type of Manuscript: Special Section PAPER (Special Section on Advanced Image Technology) Category: Keyword: MPEG-2/H.264 video transcoding, content-based, mode decision, intra prediction,
	Summary \| Full Text:PDF (671.4KB)

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3602-3612 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: low-density parity-check codes, parallel LDPC decoder architecture, message-passing algorithm, FIFO-based buffering,
	Summary \| Full Text:PDF (1018KB)

A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC Zhenyu LIU Yang SONG Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/12/01 Vol. E89-C No. 12 pp. 1928-1936 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: H.264, AVC, variable block size motion estimation, VLSI architecture,
	Summary \| Full Text:PDF (667.7KB)

A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization Yang SONG Zhenyu LIU Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3594-3601 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: variable block size motion estimation (VBSME), memory organization, H.264/AVC,
	Summary \| Full Text:PDF (503.5KB)

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 969-978 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low-density parity-check codes, partially-parallel LDPC decoder, message-passing algorithm, FPGA,
	Summary \| Full Text:PDF (749.1KB)

Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC Yang SONG Zhenyu LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 979-988 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: variable block size motion estimation (VBSME), H.264/AVC, very large scale integration (VLSI) architecture,
	Summary \| Full Text:PDF (1.4MB)

A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding Shen LI Takeshi IKENAGA Hideki TAKEDA Masataka MATSUI Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 932-940 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: content-based, motion estimation, power-efficient, real-time, MPEG-4,
	Summary \| Full Text:PDF (1.2MB)

A Contour-Based Robust Algorithm for Text Detection in Color Images Yangxing LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1221-1230 Type of Manuscript: PAPER Category: Image Recognition, Computer Vision Keyword: text detection, texture analysis, connected component analysis, region contour, edge detection,
	Summary \| Full Text:PDF (1.2MB)

A Selective Video Encryption Scheme for MPEG Compression Standard Gang LIU Takeshi IKENAGA Satoshi GOTO Takaaki BABA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/01/01 Vol. E89-A No. 1 pp. 194-202 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Application Keyword: commercial multimedia applications, selective encryption, MPEG codec, MPEG bitstream, data shuffle, processing overhead, bit overhead,
	Summary \| Full Text:PDF (525.6KB)

A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation Zhenyu LIU Yang SONG Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3523-3530 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: fast Fourier transform (FFT), array processing, singleton algorithm,
	Summary \| Full Text:PDF (1.5MB)

A Highly Parallel Architecture for Deblocking Filter in H.264/AVC Lingfeng LI Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1623-1629 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Parallel and/or Distributed Processing Systems Keyword: deblocking filter, H.264/AVC, parallel memory, adaptive filter,
	Summary \| Full Text:PDF (937.2KB)

Content-Based Motion Estimation with Extended Temporal-Spatial Analysis Shen LI Yong JIANG Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1561-1568 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Image Processing and Multimedia Systems Keyword: motion estimation, adaptive, content-based, spatial and temporal correlation,
	Summary \| Full Text:PDF (992KB)

Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1526-1537 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Adaptive Signal Processing Keyword: dynamic reconfigurable system, adaptive FEC, Reed-Solomon code with interleaving,
	Summary \| Full Text:PDF (707.5KB)