Ryota SHIOYA


Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 822-837
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorregister filemultibanking
 Summary | Full Text:PDF(3.2MB)

Applying Razor Flip-Flops to SRAM Read Circuits
Ushio JIMBO Junji YAMADA Ryota SHIOYA Masahiro GOSHIMA 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 245-258
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
random variationtiming fault detection and recoverydynamic voltage and frequency scaling (DVFS)SRAM
 Summary | Full Text:PDF(2MB)

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 232-244
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
register fileregister cachedigital designfreePDK
 Summary | Full Text:PDF(3.2MB)

FXA: Executing Instructions in Front-End for Energy Efficiency
Ryota SHIOYA Ryo TAKAMI Masahiro GOSHIMA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 1092-1107
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorhybrid in-order/out-of-order coreenergy efficiency
 Summary | Full Text:PDF(1.3MB)

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency
Ryota SHIOYA Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/03/01
Vol. E99-D  No. 3  pp. 630-640
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processorregister renamingtrace cacheenergy efficiency
 Summary | Full Text:PDF(1MB)

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control
Hideki ANDO Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/02/01
Vol. E99-D  No. 2  pp. 341-350
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsuperscalar processormemory-level parallelisminstruction-level parallelismpower consumption
 Summary | Full Text:PDF(638.6KB)

Address Order Violation Detection with Parallel Counting Bloom Filters
Naruki KURATA Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 580-593
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
processor architectureload-store queuebloom filterlow-energy technologies
 Summary | Full Text:PDF(1.8MB)

Register Indirect Jump Target Forwarding
Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2  pp. 278-288
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architectureregister indirect jumpobject-oriented programming
 Summary | Full Text:PDF(1.7MB)

Low-Overhead Architecture for Security Tag
Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 69-78
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecturetagged architectureinformation securityinformation flow tracking
 Summary | Full Text:PDF(507.1KB)