Ryohei KOBAYASHI


ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment
Shimpei SATO Ryohei KOBAYASHI Kenji KISE 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 344-353
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology and Platform
Keyword: 
hardware description languageRTL modelingRTL simulation
 Summary | Full Text:PDF(831.3KB)

A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism
Ryohei KOBAYASHI Kenji KISE 
Publication:   
Publication Date: 2017/05/01
Vol. E100-D  No. 5  pp. 1003-1015
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
sortinghardware acceleratordata compressionopen source
 Summary | Full Text:PDF(6.1MB)