Rei AKIYAMA


Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
Mitsuya FUKAZAWA  Masanori KURIMOTO  Rei AKIYAMA  Hidehiro TAKATA  Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 475-482
Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
power supply voltage noise built-in probing circuitfailure susceptibilitydynamic frequency scaling
  Summary |  Full Text:PDF (1.6MB)

Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core
Takashi KURAFUJI  Yasunobu NAKASE  Hidehiro TAKATA  Yukinaga IMAMURA  Rei AKIYAMA  Tadao YAMANAKA  Atsushi IWABU  Shutarou YASUDA  Toshitsugu MIWA  Yasuhiro NUNOMURA  Niichi ITOH  Tetsuya KAGEMOTO  Nobuharu YOSHIOKA  Takeshi SHIBAGAKI  Hiroyuki KONDO  Masayuki KOYAMA  Takahiko ARAKAWA  Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 535-542
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
resizable cacheselective-setshierarchy SRAMpartial swing
  Summary |  Full Text:PDF (794.8KB)

Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
Akira YAMADA  Yasuhiro NUNOMURA  Hiroaki SUZUKI  Hisakazu SATO  Niichi ITOH  Tetsuya KAGEMOTO  Hironobu ITO  Takashi KURAFUJI  Nobuharu YOSHIOKA  Jingo NAKANISHI  Hiromi NOTANI  Rei AKIYAMA  Atsushi IWABU  Tadao YAMANAKA  Hidehiro TAKATA  Takeshi SHIBAGAKI  Takahiko ARAKAWA  Hiroshi MAKINO  Osamu TOMISAWA  Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 635-642
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
microcontrollerhigh-speedsignal integrityIR dropdesign technique
  Summary |  Full Text:PDF (1.9MB)

Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor
Hidehiro TAKATA  Rei AKIYAMA  Tadao YAMANAKA  Haruyuki OHKUMA  Yasue SUETSUGU  Toshihiro KANAOKA  Satoshi KUMAKI  Kazuya ISHIHARA  Atsuo HANAMI  Tetsuya MATSUMURA  Tetsuya WATANABE  Yoshihide AJIOKA  Yoshio MATSUDA  Syuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 368-374
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Product Designs
Keyword: 
multimedia processorclock skewcross-talk noiseIR dropMPEG-2 encoder
  Summary |  Full Text:PDF (1.6MB)