Rafael K. MORIZAWA

SoC Architecture Synthesis Methodology Based on High-Level IPs
Michiaki MURAOKA  Hiroaki NISHI  Rafael K. MORIZAWA  Hideaki YOKOTA  Yoichi ONISHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3057-3067
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
system level design,  architecture synthesis,  high level IP,  CAD, 
  Summary |  Full Text:PDF (3.7MB)
A Specification Style of Four-Phase Handshaking Asynchronous Controllers and the Optimization of Its Return-to-Zero Phase
Rafael K. MORIZAWA  Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/20
Vol. E83-A  No. 12  pp. 2446-2455
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Methodology
Keyword: 
asynchronous circuit,  asynchronous specification,  logic synthesis,  CAD tool, 
  Summary |  Full Text:PDF (546.6KB)