Pil-Ho LEE


A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display
Ho-Seong KIM Pil-Ho LEE Jin-Wook HAN Seung-Hun SHIN Seung-Wuk BAEK Doo-Ill PARK Yongkyu SEO Young-Chan JANG 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11  pp. 1035-1038
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
transmitter bridge chipMIPI D-PHYDSIFPGA-based frame generatorphase-locked loop
 Summary | Full Text:PDF(616.5KB)

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators
Sang-Min PARK Yeon-Ho JEONG Yu-Jeong HWANG Pil-Ho LEE Yeong-Woong KIM Jisu SON Han-Yeol LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 651-654
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
asynchronous successive approximation registeranalog-to-digital convertermeta-stability detectorreplica comparator
 Summary | Full Text:PDF(1.2MB)

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis
Pil-Ho LEE Yu-Jeong HWANG Han-Yeol LEE Hyun-Bae LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/04/01
Vol. E99-C  No. 4  pp. 440-443
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
on-chip monitoring circuitchip-to-chip interfaceanalog-to-digital converterphase-locked loop-based frequency synthesizersub-sampling
 Summary | Full Text:PDF(937.6KB)

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle
Pil-Ho LEE Hyun Bae LEE Young-Chan JANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/05/01
Vol. E97-C  No. 5  pp. 463-467
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
multi-phase DLLharmonic lockcoarse-locking circuitinitial phase detectorduty cycle
 Summary | Full Text:PDF(1.3MB)