Noriyuki MINEGISHI


VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
Noriyuki MINEGISHI Junichi MIYAKOSHI Yuki KURODA Tadayoshi KATAGIRI Yuki FUKUYAMA Ryo YAMAMOTO Masayuki MIYAMA Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3  pp. 230-242
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: System LSIs and Microprocessors
Keyword: 
optical flowprocessor architecturevideo segmentation
 Summary | Full Text:PDF(4.2MB)

A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec
Noriyuki MINEGISHI Ken-ichi ASANO Keisuke OKADA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 482-490
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
heterogeneous multiple processorsmultimedia communicationH.32xMPEG-4H.26x
 Summary | Full Text:PDF(1.8MB)

A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication
Noriyuki MINEGISHI Ken-ichi ASANO Hirokazu SUZUKI Keisuke OKADA Takashi KAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1571-1578
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Debugging Multiple Processors
Keyword: 
VLSIdebug methodologyheterogeneous multiple processorIEEE 1149.1reducing debug period
 Summary | Full Text:PDF(1.7MB)