Noriyoshi ITAZAKI


Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits
Kazuya SHIMIZU Takanori SHIRAI Masaya TAKAMURA Noriyoshi ITAZAKI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1526-1533
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
domino circuitcrosstalk faulttarget fault reductionfault simulation
 Summary | Full Text:PDF(155.9KB)

A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
Noriyoshi ITAZAKI Yasutaka IDOMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1  pp. 38-43
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
crosstalk faultfault simulationsequential circuittest
 Summary | Full Text:PDF(526.4KB)

Efficient Methods for Guided-Probe Diagnosis
WEN Xiaoqing Noriyoshi ITAZAKI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 817-825
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
guided-probe diagnosisE-beam probingprobing line determination methodfault probability
 Summary | Full Text:PDF(730.6KB)