Nobutaro SHIBATA


A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications
Nobutaro SHIBATA Mayumi WATANABE Takako ISHIHARA 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11  pp. 1061-1068
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
10T memory cellCMOSdual-port SRAMFIFO memoryfully depleted SOIlook-ahead operationmulti-VDDserial access
 Summary | Full Text:PDF(1MB)

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications
Nobutaro SHIBATA Yoshinori GOTOH Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 717-726
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
10T typebitline capacitanceCMOSgate arrayhigh speedlow powermemory-oriented base cellshared contacttwo-port SRAM
 Summary | Full Text:PDF(1.7MB)

A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme
Nobutaro SHIBATA Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C  No. 2  pp. 316-330
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
4-way set-associativecache-tagCMOSdirected graphdual-rail wordlineFD-SOII/O-separated memory cellLRUNRZ-type write-enable signalSIMOXSRAM
 Summary | Full Text:PDF(1.5MB)

A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation
Takakuni DOUSEKI Toshishige SHIMAMURA Nobutaro SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 582-588
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
ultralow voltagehigh-speedED-MOSmulti-Vth CMOSfully-depleted SOI
 Summary | Full Text:PDF(877.2KB)

Current-Sensed SRAM Techniques for Megabit-Class Integration--Progress in Operating Frequency by Using Hidden Writing-Recovery Architecture--
Nobutaro SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Vol. E82-C  No. 11  pp. 2056-2064
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMhigh speedwriting-recoverycurrent sensevirtual-GND linesquashed memory cell
 Summary | Full Text:PDF(1.6MB)

Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1  pp. 94-104
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMmacrocellsize-configurablehigh speedlow powerper-bitline architecturecurrent-sense amplifiersquashed memory celltrench isolation
 Summary | Full Text:PDF(931.1KB)

A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's
Nobutaro SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12  pp. 1598-1607
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMlow powervirtual GNDcolumn addresssynchronousmacrocell
 Summary | Full Text:PDF(774.4KB)

Current Sense Amplifiers for Low-Voltage Memories
Nobutaro SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/08/25
Vol. E79-C  No. 8  pp. 1120-1130
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMROMcurrent sensingamplifierlow voltage
 Summary | Full Text:PDF(888.7KB)

A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA Mayumi WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 797-804
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
marcocellmemorysynchronouslow powerlatch type
 Summary | Full Text:PDF(712KB)

High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1641-1648
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
ASICCMOSmacrocellmemoryconfigurablerow sliceabledecodershort design Turn-Around-Time (TAT)
 Summary | Full Text:PDF(692.2KB)