Nobuhiro TOMABECHI

Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs
Yoshichika FUJIOKA  Michitaka KAMEYAMA  Nobuhiro TOMABECHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/20
Vol. E77-C  No. 7  pp. 1123-1130
Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
delay time,  multi-operand multiply-addition,  reconfiguration,  digital control,  FPGA, 
  Summary |  Full Text:PDF (675.2KB)
Fault-Tolerant Digital Filters Using Pulse-Train Residue Arithmetic Circuits
Moon Soo KIM  Nobuhiro TOMABECHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/10/20
Vol. E70-E  No. 10  pp. 1009-1017
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword: 
  Summary |  Full Text:PDF (743.9KB)