Nobuhiro DOI


Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3427-3434
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
HDLhigh-level synthesisbit-length optimizationnon-linear programming
 Summary | Full Text:PDF(315KB)

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3184-3191
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
HDLhigh-level synthesisparallelizing compilerbit length
 Summary | Full Text:PDF(863.4KB)