Nobuaki TOJO


A Two-Level Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3238-3247
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
two-level cacheL1/L2cache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF(522.3KB)

An L1 Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6  pp. 1442-1453
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
cachecache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF(1.1MB)