Noboru AKIYAMA

High Speed Data Output Circuit Techniques for a 17 ns 4 Mbit BiCMOS DRAM
Hitoshi MIWA  Shoji WADA  Yuji YOKOYAMA  Masayuki NAKAMURA  Tatsuyuki OHTA  Toshio MAEDA  Masahiro YOSHIDA  Hideuki MIYAZAWA  Noboru AKIYAMA  Kazuyuki MIYAZAWA  Jun MURATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/20
Vol. E75-C  No. 11  pp. 1344-1350
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
BiCMOS,  noise immune,  data sense,  level shift, 
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