Naofumi TAKAGI


Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication
Nobutaka KITO Kazushi AKIMOTO Naofumi TAKAGI 
Publication:   
Publication Date: 2017/03/01
Vol. E100-D  No. 3  pp. 531-536
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
concurrent error detectionfloating-point multiplierduplicationtruncated multiplier
 Summary | Full Text:PDF(512.4KB)

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
Masamitsu TANAKA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 703-709
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
digital arithmeticdigit-serial processinghardware algorithmrapid single-flux-quantum logicsigned-digit representationsystolic array
 Summary | Full Text:PDF(471.1KB)

RSFQ 4-bit Bit-Slice Integer Multiplier
Guang-Ming TANG Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 697-702
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
multipliersingle-flux-quantum (SFQ)microprocessorsuperconducting integrated circuits
 Summary | Full Text:PDF(2MB)

A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model
Takahiro KAWAGUCHI Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2556-2564
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
single-flux-quantum circuitstatic timing analysisformal verification
 Summary | Full Text:PDF(1.1MB)

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis
Akihiro SUDA Hideki TAKASE Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2498-2506
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisarray partitioningbuffer managementPolyhedral Optimization
 Summary | Full Text:PDF(1.2MB)

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process
Xizhu PENG Yuki YAMANASHI Nobuyuki YOSHIKAWA Akira FUJIMAKI Naofumi TAKAGI Kazuyoshi TAKAGI Mutsuo HIDAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 188-193
Type of Manuscript:  Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
floating point unitmultiplierLSRDPSFQ circuitsuperconductive integrated circuit
 Summary | Full Text:PDF(2.2MB)

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits
Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 149-156
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologycircuit descriptionlogic designlayout designdesign verification
 Summary | Full Text:PDF(2.8MB)

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits
Hiroshi KATAOKA Hiroaki HONDA Farhad MEHDIPOUR Nobuyuki YOSHIKAWA Akira FUJIMAKI Hiroyuki AKAIKE Naofumi TAKAGI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 141-148
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single flux quantumreconfigurable data-pathaccelerator
 Summary | Full Text:PDF(2MB)

Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation
Shuichi NAGASAWA Kenji HINODE Tetsuro SATOH Mutsuo HIDAKA Hiroyuki AKAIKE Akira FUJIMAKI Nobuyuki YOSHIKAWA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 132-140
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
superconducting fabrication technologyNb/AlOx/Nb Josephson junctionsingle flux quantumplanarizationshift register
 Summary | Full Text:PDF(5.3MB)

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors
Akira FUJIMAKI Masamitsu TANAKA Ryo KASAGI Katsumi TAKAGI Masakazu OKADA Yuhi HAYAKAWA Kensuke TAKATA Hiroyuki AKAIKE Nobuyuki YOSHIKAWA Shuichi NAGASAWA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3  pp. 157-165
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
advanced processcell-based design techniquehigh-end computinglarge-scale integrationrapid single-flux-quantum circuits
 Summary | Full Text:PDF(2.3MB)

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication
Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1962-1970
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
parity predictionparallel prefix adderfault securecarry-bit duplication
 Summary | Full Text:PDF(968.9KB)

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
Kazuhiro NAKAMURA Ryo SHIMAZAKI Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 456-467
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architectureisolated word recognition
 Summary | Full Text:PDF(2.3MB)

A C-Testable Multiple-Block Carry Select Adder
Nobutaka KITO Shinichi FUJII Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4  pp. 1084-1092
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
carry select adderdesign for testabilityC-testability
 Summary | Full Text:PDF(311.2KB)

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
Kazuyoshi TAKAGI Yuki ITO Shota TAKESHIMA Masamitsu TANAKA Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3  pp. 288-295
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologyclock tree synthesisclock skew
 Summary | Full Text:PDF(1.1MB)

A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
Nobutaka KITO Kensuke HANAI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10  pp. 2783-2791
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
multiplierdesign for testability4-2 adder treeC-testability
 Summary | Full Text:PDF(381.2KB)

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process
Yuki YAMANASHI Toshiki KAINUMA Nobuyuki YOSHIKAWA Irina KATAEVA Hiroyuki AKAIKE Akira FUJIMAKI Masamitsu TANAKA Naofumi TAKAGI Shuichi NAGASAWA Mutsuo HIDAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/04/01
Vol. E93-C  No. 4  pp. 440-444
Type of Manuscript:  Special Section PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: Digital Applications
Keyword: 
single flux quantum circuitJosephson junctioncell libraryadder
 Summary | Full Text:PDF(668.8KB)

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm
Masamitsu TANAKA Koji OBATA Yuki ITO Shota TAKESHIMA Motoki SATO Kazuyoshi TAKAGI Naofumi TAKAGI Hiroyuki AKAIKE Akira FUJIMAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/04/01
Vol. E93-C  No. 4  pp. 435-439
Type of Manuscript:  Special Section PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: Digital Applications
Keyword: 
single-flux-quantum circuitcomputer-aided designwire routerpassive transmission line
 Summary | Full Text:PDF(970.9KB)

Comparisons of Synchronous-Clocking SFQ Adders
Naofumi TAKAGI Masamitsu TANAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/04/01
Vol. E93-C  No. 4  pp. 429-434
Type of Manuscript:  INVITED PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: 
Keyword: 
single-flux-quantum (SFQ) circuitadderhardware algorithm
 Summary | Full Text:PDF(274.2KB)

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
Kazuhiro NAKAMURA Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/02/01
Vol. E93-D  No. 2  pp. 300-305
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architecture
 Summary | Full Text:PDF(549KB)

A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3772-3782
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock schedulingclock skewmicropipelineRSFQ
 Summary | Full Text:PDF(460.1KB)

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits
Naofumi TAKAGI Kazuaki MURAKAMI Akira FUJIMAKI Nobuyuki YOSHIKAWA Koji INOUE Hiroaki HONDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3  pp. 350-355
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics)
Category: 
Keyword: 
superconductorrapid single-flux-quantum circuitreconfigurable data-pathhigh-performance computingsupercomputer
 Summary | Full Text:PDF(297.2KB)

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/12/01
Vol. E90-C  No. 12  pp. 2278-2284
Type of Manuscript:  PAPER
Category: Superconducting Electronics
Keyword: 
sequential circuit synthesisone-hot encodingsingle-flux-quantum (SFQ)
 Summary | Full Text:PDF(255.3KB)

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams
Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 257-266
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic synthesisdual-railRSFQbinary decision diagrams (BDDs)
 Summary | Full Text:PDF(462.9KB)

A Hardware Algorithm for Integer Division Using the SD2 Representation
Naofumi TAKAGI Shunsuke KADOWAKI Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/10/01
Vol. E89-A  No. 10  pp. 2874-2881
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticdivisioninteger divisionhardware algorithmsigned-digit representationVLSI
 Summary | Full Text:PDF(377.5KB)

Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector
Fumio KUMAZAWA Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6  pp. 1799-1806
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmetichardware algorithmreciprocal of the Euclidean normdigit-recurrencecomputer graphics
 Summary | Full Text:PDF(260.2KB)

A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm
Marcelo E. KAIHARA Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3610-3617
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
modular arithmeticmodular multiplicationmodular divisionMontgomery multiplicationextended Euclidean algorithmhardware algorithm
 Summary | Full Text:PDF(208KB)

Digit-Recurrence Algorithm for Computing Reciprocal Square-Root
Naofumi TAKAGI Daisuke MATSUOKA Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/01/01
Vol. E86-A  No. 1  pp. 221-228
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticreciprocal square-roothardware algorithmdigit-recurrencecomputer graphics
 Summary | Full Text:PDF(229.7KB)

A VLSI Algorithm for Division in GF(2m) Based on Extended Binary GCD Algorithm
Yasuaki WATANABE Naofumi TAKAGI Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/05/01
Vol. E85-A  No. 5  pp. 994-999
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
finite field arithmeticdivision in finite fieldhardware algorithmVLSI algorithm
 Summary | Full Text:PDF(234.2KB)

A Digit-Recurrence Algorithm for Cube Rooting
Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5  pp. 1309-1314
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticcube rootinghardware algorithmdigit-recurrence algorithmVLSI
 Summary | Full Text:PDF(255.2KB)

Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees
Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5  pp. 767-774
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithmminimum cut linear arrangementVLSI layoutadder treemultiplier
 Summary | Full Text:PDF(690KB)

A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm
Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 724-728
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
modular arithmeticmodular divisionGCDhardware algorithmredundant representation
 Summary | Full Text:PDF(379.3KB)

A Hardware Algorithm for Modular Division Based on the Extended Euclidean Algorithm
Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11  pp. 1518-1522
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
Euclidean algorithmhardware algorithmmodular arithmeticmodular divisionredundant representation
 Summary | Full Text:PDF(404.8KB)

A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions
Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/10/25
Vol. E78-D  No. 10  pp. 1313-1315
Type of Manuscript:  LETTER
Category: Algorithm and Computational Complexity
Keyword: 
algorithmcard computermodular arithmeticpublic-key cryptograph
 Summary | Full Text:PDF(184.5KB)

A Modular Inversion Hardware Algorithm with a Redundant Binary Representation
Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/08/25
Vol. E76-D  No. 8  pp. 863-869
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer arithmeticcomputer cryptographgreatest common divisor (GCD)hardware algorithmmodular arithmetic
 Summary | Full Text:PDF(532.9KB)