Nagisa ISHIURA


CF3: Test Suite for Arithmetic Optimization of C Compilers
Yusuke HIBINO Hirofumi IKEO Nagisa ISHIURA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1511-1512
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
C compiler test suitearithmetic optimization
 Summary | Full Text:PDF(57.6KB)

High-Level Synthesis of Software Function Calls
Masanari NISHIMURA Nagisa ISHIURA Yoshiyuki ISHIMORI Hiroyuki KANBARA Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3556-3558
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisCCAPhardware/software co-designC-based design
 Summary | Full Text:PDF(308.9KB)

FOREWORD
Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3413-3414
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF(49.2KB)

Register Constraint Analysis to Minimize Spill Code for Application Specific DSPs
Tatsuo WATANABE Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6  pp. 1541-1544
Type of Manuscript:  Special Section LETTER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
application specific DSPspill code insertionembedded systemschedulingregister constraint analysis
 Summary | Full Text:PDF(588.6KB)

Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes
Mizuki TAKAHASHI Nagisa ISHIURA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2456-2463
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design and High-level Synthesis
Keyword: 
behavioral partitioningthread compositionbehavioral synthesis
 Summary | Full Text:PDF(671.1KB)

A Binding Algorithm for Retargetable Compilation to Non-orthogonal DSP Architectures
Masayuki YAMAGUCHI Nagisa ISHIURA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12  pp. 2630-2639
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
retargetable compilerbindingnon-orthogonal architectureDSPbinary decision diagram
 Summary | Full Text:PDF(869.9KB)

Embedded Memory Array Testing Using a Scannable Configuration
Seiken YANO Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1934-1944
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
scannable memory configurationmemory array testingdesign-for-testabilityscan design
 Summary | Full Text:PDF(823.2KB)

Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Masayuki YAMAGUCHI Akihisa YAMADA Toshihiro NAKAOKA Takashi KAMBE Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1853-1860
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance evaluationdatapathstructureparallel constraint
 Summary | Full Text:PDF(751.3KB)

Application of Full Scan Design to Embedded Memory Arrays
Seiken YANO Katsutoshi AKAGI Hiroki INOHARA Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 514-520
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
design-for-testabilityDFT scan designscannable memory arraymemory array testing
 Summary | Full Text:PDF(621.8KB)

Implicit Representation and Manipulation of Binary Decision Diagrams
Hitoshi YAMAUCHI Nagisa ISHIURA Hiromitsu TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3  pp. 354-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
binary decision diagram (BDD)representation of Boolean functionslogic design verificationlogic synthesisimplicit representation of graphs
 Summary | Full Text:PDF(747KB)

Datapath Scheduling for Behavioral Description with Conditional Branches
Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 1999-2009
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesisdatapath scheduling0-1 integer programming problembinary decision diagrambranch-and-bound method
 Summary | Full Text:PDF(902.6KB)

Test Generation for Sequential Circits Using Partitioned Image Computation
Hoyong CHOI Hironori MAEDA Takashi KOHARA Nagisa ISHIURA Isao SHIRAKAWA Akira MOTOHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1770-1774
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test generation for sequential circuittproduct machine traversal methodmixed breadth-first/depth-first traversalpartitioned image computation
 Summary | Full Text:PDF(350.1KB)

Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1121-1127
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
test generationcombinational circuitscompact test setsbinary decision diagrams
 Summary | Full Text:PDF(661.1KB)

Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams
Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9  pp. 1085-1092
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesisbinary decision diagramscombinational circuits
 Summary | Full Text:PDF(647.1KB)

Research Topics and Results on Simulation for VLSI
Isao SHIRAKAWA Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A  No. 7  pp. 1070-1076
Type of Manuscript:  Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)
Category: 
Keyword: 
VLSIcircuit simulationlogic simulation
 Summary | Full Text:PDF(717.3KB)

Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits
Nagisa ISHIURA Yutaka DEGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1247-1254
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic circuitstiming verificationsymbolic simulationBoolean function manipulation
 Summary | Full Text:PDF(636.9KB)

Linear Time Fault Simulation Algorithm Using a Content Addressable Memory
Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3  pp. 314-320
Type of Manuscript:  INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
fault simulationcontent addressable memoryparallel computation
 Summary | Full Text:PDF(539.6KB)