IEICE SEARCH SYSTEM

Moritoshi YASUNAGA

A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic Hung Dinh NGUYEN Ikuo YOSHIHARA Kunihito YAMAMORI Moritoshi YASUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/10/01 Vol. E90-A No. 10 pp. 2187-2193 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Optimization Keyword: traveling salesman problem, Lin-Kernighan heuristic, data structure, three-level trees,
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Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification Hanxi ZHU Ikuo YOSHIHARA Kunihito YAMAMORI Moritoshi YASUNAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/07/01 Vol. E87-D No. 7 pp. 1943-1952 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: multi-modal neural network, symbolic sequence pattern classification, majority decision, English pronunciation reasoning, prediction of protein secondary structure,
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The Evolutionary Algorithm-Based Reasoning System Moritoshi YASUNAGA Ikuo YOSHIHARA Jung Hwan KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-D No. 11 pp. 1508-1520 Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems) Category: Keyword: evolutionary algorithm, reasoning, FPGA, wafer scale integration, fault tolerance,
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The Kernel-Based Pattern Recognition System Designed by Genetic Algorithms Moritoshi YASUNAGA Taro NAKAMURA Ikuo YOSHIHARA Jung Hwan KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-D No. 11 pp. 1528-1539 Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems) Category: Keyword: genetic algorithm, FPGA, pattern recognition, reconfigurable system, kernel-based method,
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Performance Evaluation of Neural Network Hardware Using Time-Shared Bus and Integer Representation Architecture Moritoshi YASUNAGA Tatsuo OCHIAI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/06/20 Vol. E79-D No. 6 pp. 888-896 Type of Manuscript: PAPER Category: Bio-Cybernetics and Neurocomputing Keyword: neural networks, parallel computing, parallel programming language, performance evaluation, scalability,
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Robustness of the Memory-Based Reasoning Implemented by Wafer Scale Integration Moritoshi YASUNAGA Hiroaki KITANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/03/20 Vol. E76-D No. 3 pp. 336-344 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault tolerant computing, artificial intelligence and computer hardware design,
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