Mitsuo SONEDA


5. 4 GOPS, 81 GB/s Linear Array Architecture DSP
Akihiko HASHIGUCHI  Masuyoshi KUROKAWA  Ken'ichiro NAKAMURA  Hiroshi OKUDA  Koji AOYAMA  Mitsuharu OHKI  Katsunori SENO  Ichiro KUMATA  Masatoshi AIKAWA  Hirokazu HANAKI  Takao YAMAZAKI  Mitsuo SONEDA  Seiichiro IWASE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/20
Vol. E81-C  No. 5  pp. 661-668
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
videoparallel processingSIMDDSP
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