Michitaka OKUNO


Design and Evaluation of 10 Gbps Optical Access System Using Optical Switches
Koji WAKAYAMA Michitaka OKUNO Jun SUGAWA Daisuke MASHIMO Hiroki IKEDA Kenichi SAKAMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/02/01
Vol. E93-B  No. 2  pp. 272-279
Type of Manuscript:  Special Section PAPER (Special Section on Optical Access Technologies)
Category: 
Keyword: 
optical switch controlactive optical access systemoptical switching unitFEC10G-EPON
 Summary | Full Text:PDF(1.5MB)

A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Matsuaki TERADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1957-1963
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
EthernetVSRbackplaneskewFECFire codes
 Summary | Full Text:PDF(1.3MB)

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic
Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1620-1628
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
100-Gbps Ethernetnetwork processorcachenetwork trafficlow power
 Summary | Full Text:PDF(1.7MB)

100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Kouji FUKUDA Kouji NAKAHARA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/03/01
Vol. E89-B  No. 3  pp. 696-703
Type of Manuscript:  Special Section PAPER (Special Section on the Next Generation Ethernet Technologies)
Category: 
Keyword: 
EthernetMANskewFEC
 Summary | Full Text:PDF(1.8MB)

Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router
Michitaka OKUNO Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
routerEthernetpacket-processing enginenetwork processorcache-based packet-processing engine
 Summary | Full Text:PDF(383.1KB)