IEICE SEARCH SYSTEM

Michitaka KAMEYAMA

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation Yoshitaka HIRAMATSU Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Toru NOJIRI Kunio UCHIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 pp. 1872-1882 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: block matching, heterogeneous multi-core, dynamically reconfigurable processor, data transfer, accelerator,
	Summary \| Full Text:PDF (4.4MB)

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates Zhengfan XIA Shota ISHIHARA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/08/01 Vol. E95-C No. 8 pp. 1434-1443 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: asynchronous pipeline, dual-rail, critical datapath,
	Summary \| Full Text:PDF (2.1MB)

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors Hasitha Muthumala WAIDYASOORIYA Yosuke OHBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 354-363 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: memory allocation, partitioning, reconfigurable processors,
	Summary \| Full Text:PDF (845.4KB)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/10/01 Vol. E94-C No. 10 pp. 1669-1679 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: mixed synchronous/asynchronous design, reconfigurable VLSI, four-phase dual-rail encoding, self-timed architecture, GALS (Globally Asynchronous Locally Synchronous),
	Summary \| Full Text:PDF (3.4MB)

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 342-351 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: memory allocation, parallel data access, addressing,
	Summary \| Full Text:PDF (2MB)

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation Hasitha Muthumala WAIDYASOORIYA Daisuke OKUMURA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2570-2580 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: heterogeneous multi-core processor, task-allocation, system-on-chip,
	Summary \| Full Text:PDF (1.3MB)

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals Shota ISHIHARA Noriaki IDOBATA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2134-2144 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Application of Multiple-Valued VLSI Keyword: dynamically programmable gate array, multi-context switch, logic-in-memory circuit, multiple-valued threshold logic, nonvolatile storage, non-destructive operation,
	Summary \| Full Text:PDF (2.1MB)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture Shota ISHIHARA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/08/01 Vol. E93-C No. 8 pp. 1338-1348 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: reconfigurable VLSI, field-programmable VLSI, LEDR (Level-Encoded Dual-Rail) encoding, 4-phase dual-rail encoding, self-timed architecture,
	Summary \| Full Text:PDF (1.6MB)

FOREWORD Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2025-2025 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF (53KB)

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits Nobuaki OKADA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2126-2133 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Application of Multiple-Valued VLSI Keyword: multiple-valued current-mode logic, fine-grain reconfigurable VLSI, direct allocation, control circuit, sequential logic circuit,
	Summary \| Full Text:PDF (789KB)

Group Testing Based Detection of Web Service DDoS Attackers Dalia NASHAT Xiaohong JIANG Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2010/05/01 Vol. E93-B No. 5 pp. 1113-1121 Type of Manuscript: Special Section PAPER (Special Section on Technology and Architecture for Sustainable Growth of the Internet) Category: Keyword: distributed denial of service, group-testing, intrusion detection, change point detection,
	Summary \| Full Text:PDF (4.4MB)

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 539-549 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DPGA, multi-context, asynchronous FPGA,
	Summary \| Full Text:PDF (1.8MB)

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3596-3606 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, low power, interconnection network, genetic algorithm,
	Summary \| Full Text:PDF (1.2MB)

Memory Allocation for Multi-Resolution Image Processing Yasuhiro KOBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/10/01 Vol. E91-D No. 10 pp. 2386-2397 Type of Manuscript: PAPER Category: VLSI Systems Keyword: high-level synthesis, interconnection-aware architecture, stereo vision,
	Summary \| Full Text:PDF (635.7KB)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1419-1426 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: FPGAs, reconfigurable VLSIs, asynchronous architecture, LEDR (Level-Encoded Dual-Rail) encoding,
	Summary \| Full Text:PDF (661.8KB)

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation Nobuaki OKADA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1437-1443 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: fine-grain reconfigurable VLSI, multiple-valued source-coupled logic, universal literal, direct allocation of CDFG, logic block,
	Summary \| Full Text:PDF (879.1KB)

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling Masanori HARIYAMA Naoto YOKOYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 479-486 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: stereo vision, scheduling, allocation,
	Summary \| Full Text:PDF (1020.3KB)

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment Hasitha Muthumala WAIDYASOORIYA Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 517-525 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: dynamically-programmable gate array, multi-context FPGA, configuration data redundancy,
	Summary \| Full Text:PDF (1.5MB)

FOREWORD Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1849-1849 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF (59.9KB)

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates Masanori HARIYAMA Sho OGATA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1655-1661 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: time-multiplexed FPGA, dynamically reconfigurable architecture, DPGA, bit-serial architecture,
	Summary \| Full Text:PDF (867.1KB)

Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1551-1558 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: automatic synthesis, scheduling, module selection, data-path design, optimization,
	Summary \| Full Text:PDF (1.2MB)

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3298-3305 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: reconfigurable processor, FPGA, multiple-supply-voltage scheme,
	Summary \| Full Text:PDF (924.7KB)

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3516-3522 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: stereo vision, FPGA, scheduling, allocation,
	Summary \| Full Text:PDF (813.5KB)

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access Masanori HARIYAMA Haruka SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1486-1491 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: stereo vision, SAD (sum of absolute differences), memory allocation, logic-in-memory architecture,
	Summary \| Full Text:PDF (1.1MB)

Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic Md.Munirul HAQUE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1869-1875 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable processor, multiple-valued logic, bit-serial architecture, current mode logic,
	Summary \| Full Text:PDF (606.4KB)

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1897-1902 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable architecture, FPGA, bit-serial architecture,
	Summary \| Full Text:PDF (530.6KB)

Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/10/01 Vol. E85-C No. 10 pp. 1814-1823 Type of Manuscript: PAPER Category: Optoelectronics Keyword: interconnection problem, pass-transistor network, functional pass gate, multiple-valued logic, content-addressable memory,
	Summary \| Full Text:PDF (1.5MB)

Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 288-296 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: pass-transistor network, functional pass gate, precharge-evaluate logic, multiplier, signed-digit adder,
	Summary \| Full Text:PDF (1.6MB)

Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme Masanori HARIYAMA Seunghwan LEE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/03/01 Vol. E84-C No. 3 pp. 382-389 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: motion stereo, memory allocation, functional-unit allocation,
	Summary \| Full Text:PDF (2.5MB)

An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/12/20 Vol. E83-D No. 12 pp. 2122-2130 Type of Manuscript: PAPER Category: Image Processing, Image Pattern Recognition Keyword: motion stereo, FPGA-based processor, memory allocation, functional unit allocation,
	Summary \| Full Text:PDF (1.9MB)

Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory Masanori HARIYAMA Kazuhiro SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1722-1729 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Processors Keyword: hierarchical collision detection, area-time product minimization, CAM, path planning,
	Summary \| Full Text:PDF (1.4MB)

Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1662-1668 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Non-Binary Architectures Keyword: pass-transistor network, floating-gate MOS transistor, logic-in-memory structure, Manhattan distance, flash EEPROM technology, four-valued full adder,
	Summary \| Full Text:PDF (1.6MB)

A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme Seunghwan LEE Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/11/20 Vol. E80-C No. 11 pp. 1491-1498 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 3-D instrumentation, epipolar constraint, block matching algorithm, special-purpose VLSI processor, memory interleaving,
	Summary \| Full Text:PDF (645.8KB)

Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control Takahiro HANYU Satoshi KAZAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 941-947 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multiple-Valued Architectures Keyword: 54-bit multiplier, signed-digit arithmetic, differential logic circuit, threshold detector, source-coupled pair, multi-phase clocking,
	Summary \| Full Text:PDF (600.8KB)

Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing Takahiro HANYU Manabu ARAKAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 948-955 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multiple-Valued Architectures Keyword: logic value conversion (LVC), floating-gate MOS transistor, threshold operation, single-transistor cell, fully parallel template matching,
	Summary \| Full Text:PDF (571.9KB)

Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate Xiaowei DENG Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/08/20 Vol. E78-D No. 8 pp. 951-958 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, super pass gate, logic design, quantum devices, super pass transistor model,
	Summary \| Full Text:PDF (698.5KB)

High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems Yasuaki SAWANO Bumchul KIM Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/20 Vol. E77-C No. 7 pp. 1101-1107 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: intelligent integrated systems, high-level synthesis, parallel processing, minimum latency, scheduling,
	Summary \| Full Text:PDF (570KB)

Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs Yoshichika FUJIOKA Michitaka KAMEYAMA Nobuhiro TOMABECHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/20 Vol. E77-C No. 7 pp. 1123-1130 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: delay time, multi-operand multiply-addition, reconfiguration, digital control, FPGA,
	Summary \| Full Text:PDF (675.2KB)

FOREWORD Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/20 Vol. E77-C No. 7 pp. 1021-1022 Type of Manuscript: FOREWORD Category: Keyword:
	Summary \| Full Text:PDF (108.6KB)

A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition Yoshifumi SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/20 Vol. E77-C No. 7 pp. 1116-1122 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: special-purpose VLSI, visual feedback, image matching, perspective projection, highly parallel processing,
	Summary \| Full Text:PDF (611.9KB)

A Collision Detection Processor for Intelligent Vehicles Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/20 Vol. E76-C No. 12 pp. 1804-1811 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: special-purpose VLSI, content-addressable memory, rectangular solid representation,
	Summary \| Full Text:PDF (651.9KB)

Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits Saneaki TAMAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1112-1118 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: multiple-valued coding, locally computable combinational circuits, k-ary operations, partition theory, redundant coding,
	Summary \| Full Text:PDF (523.3KB)

Design of Highly Parallel Linear Digital System for ULSI Processors Masami NAKAJIMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1119-1125 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: locally computable combinational circuits, linear digital circuits, code assignment, unary operations,
	Summary \| Full Text:PDF (453.9KB)

Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model Takahiro HANYU Yoshikazu YABE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1126-1132 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: resonant-tunneling diode model, universal literal, load line method, multiple-valued PLA, wired logic, current-mode linear summation,
	Summary \| Full Text:PDF (522KB)

A Minimum-Latency Linear Array FFT Processor for Robotics Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/06/20 Vol. E76-D No. 6 pp. 680-688 Type of Manuscript: PAPER Category: Speech Processing Keyword: FFT, correlation, robotics, minimum latency, linear array processor,
	Summary \| Full Text:PDF (631.5KB)

Unified Scheduling of High Performance Parallel VLSI Processors for Robotics Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/20 Vol. E76-A No. 6 pp. 904-910 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Parallel Processor Scheduling Keyword: minimum-latency architecture, special-purpose VLSI processor, parallel processing, communication time, bus interconnection network,
	Summary \| Full Text:PDF (516.3KB)

Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory Saneaki TAMAKI Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/20 Vol. E76-D No. 5 pp. 548-554 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic Design Keyword: multiple-valued coding, locally computable circuit, unary operation, partition theory, closed chain set,
	Summary \| Full Text:PDF (502.2KB)

Prospects of Multiple-Valued VLSI Processors Takahiro HANYU Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 383-392 Type of Manuscript: INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: submicron VLSI, interconnection delay, multiple-valued hardware algorithm, parallel VLSI processor, MVL arithmetic and logic circuits,
	Summary \| Full Text:PDF (982.7KB)

Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 455-462 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiple-valued MOS current-mode circuit, residue number system, latency, parallel processing, robot vision,
	Summary \| Full Text:PDF (739.2KB)

Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements Katsuhiko SHIMABUKURO Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 463-471 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: fine-grain parallel processing, signed-digit arithmetic system, multiple-valued circuit technology, bidirectional current-mode circuits,
	Summary \| Full Text:PDF (626.4KB)

Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation Takeshi KASUGA Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 428-435 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: robust-fault-tolerant arithmetic circuit, bitonic sorter three-valued distributed coding, safety, scaler multiple-valued current-mode circuit,
	Summary \| Full Text:PDF (759.9KB)

Design of a Multiple-Valued VLSI Processor for Digital Control Katsuhiko SHIMABUKURO Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/09/20 Vol. E75-D No. 5 pp. 709-717 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: parallel-structure-based VLSI processor, signed-digit arithmetic system, multiple-valued circuit technology, bidirectional current-mode circuits,
	Summary \| Full Text:PDF (641.9KB)

Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/06/20 Vol. E75-A No. 6 pp. 712-719 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91)) Category: Robot Electronics Keyword: minimum-delay-time architecture, VLSI processor for robotics, parallel processing, parallel communication, multiple bus interconnection networks,
	Summary \| Full Text:PDF (556.5KB)

Highly Parallel Collision Detection Processor for Intelligent Robots Michitaka KAMEYAMA Tadao AMADA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/04/20 Vol. E75-C No. 4 pp. 398-404 Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
	Summary \| Full Text:PDF (574.1KB)

A Special-Purpose LSI for Inverse Kinematics Computation Michitaka KAMEYAMA Takao MATSUMOTO Hideki EGAMI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/11/20 Vol. E74-C No. 11 pp. 3829-3837 Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Dedicated Processors Keyword:
	Summary \| Full Text:PDF (855.2KB)

Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1991/11/20 Vol. E74-C No. 11 pp. 3819-3828 Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor) Category: Dedicated Processors Keyword:
	Summary \| Full Text:PDF (824.2KB)

A VLSI-Oriented Digital Signal Processor Based on Pulse-Train Residue Arithmetic Circuit with a Multiplier Michitaka KAMEYAMA Oluwole ADEGBENRO Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1985/01/20 Vol. E68-E No. 1 pp. 14-21 Type of Manuscript: PAPER Category: Signal Processing Keyword:
	Summary \| Full Text:PDF (538.7KB)