Michihiro KOIBUCHI


Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface
Hiroshi NAKAHARA Tomoya OZAKI Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2871-2880
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
inductive coupling interconnectinterconnection networknetwork on chip
 Summary | Full Text:PDF(1.7MB)

Job Mapping and Scheduling on Free-Space Optical Networks
Yao HU Ikki FUJIWARA Michihiro KOIBUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11  pp. 2694-2704
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
job mappinginterconnection networksfree-space opticshigh-performance computing
 Summary | Full Text:PDF(1MB)

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems
Akram BEN AHMED Hiroki MATSUTANI Michihiro KOIBUCHI Kimiyoshi USAMI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8  pp. 909-917
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
Network-on-Chipsmulti-Vddlow power networks
 Summary | Full Text:PDF(797.3KB)

Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks
Thao-Nguyen TRUONG Khanh-Van NGUYEN Ikki FUJIWARA Michihiro KOIBUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/05/01
Vol. E99-D  No. 5  pp. 1275-1284
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
Network expandabilitynetwork topologiessmall-world networksinterconnection networkshigh-performance computing
 Summary | Full Text:PDF(1.3MB)

The Case for Network Coding for Collective Communication on HPC Interconnection Networks
Ahmed SHALABY Ikki FUJIWARA Michihiro KOIBUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/03/01
Vol. E98-D  No. 3  pp. 661-670
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
interconnection networkscollective communicationnetwork codinghigh-performance computing
 Summary | Full Text:PDF(1.7MB)

New Directions for a Japanese Academic Backbone Network
Shigeo URUSHIDANI Shunji ABE Kenjiro YAMANAKA Kento AIDA Shigetoshi YOKOYAMA Hiroshi YAMADA Motonori NAKAMURA Kensuke FUKUDA Michihiro KOIBUCHI Shigeki YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/03/01
Vol. E98-D  No. 3  pp. 546-556
Type of Manuscript:  INVITED PAPER (Special Section on the Architectures, Protocols, and Applications for the Future Internet)
Category: 
Keyword: 
100-Gigabit EthernetMPLS-TPSDNmulti-layer networksecuritycloud serviceperformance acceleratornetwork monitoring
 Summary | Full Text:PDF(2.8MB)

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation
Ahmadou Dit Adi CISSE Michihiro KOIBUCHI Masato YOSHIMI Hidetsugu IRIE Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12  pp. 2545-2554
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
Network-on-Chiphigh-bandwidth and low power networkoptical interconnectwavelength allocation
 Summary | Full Text:PDF(1.1MB)

A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/04/01
Vol. E92-D  No. 4  pp. 575-583
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
network-on-chipFPGAcustomizerouter
 Summary | Full Text:PDF(491KB)

A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12  pp. 1914-1922
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
Networks-on-ChipFPGArouterport combination
 Summary | Full Text:PDF(467.3KB)

Architectural Design of Next-Generation Science Information Network
Shigeo URUSHIDANI Shunji ABE Kensuke FUKUDA Jun MATSUKATA Yusheng JI Michihiro KOIBUCHI Shigeki YAMADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/05/01
Vol. E90-B  No. 5  pp. 1061-1070
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Transfer Technologies for the Next Generation Network)
Category: 
Keyword: 
hybrid networkmulti-layer networkbandwidth on demandL1VPNGFPVCATLCASGMPLSMPLS
 Summary | Full Text:PDF(1.7MB)

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing
Michihiro KOIBUCHI Akiya JOURAKU Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/01/01
Vol. E88-D  No. 1  pp. 109-118
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
output selection functionadaptive routingvirtual channelinterconnection networksmassively parallel computers
 Summary | Full Text:PDF(525KB)