Masayuki TERAI

A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
Keiichi SUEMITSU  Toshiaki ITO  Toshiki KANAMOTO  Masayuki TERAI  Satoshi KOTANI  Shigeo SAWADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12  pp. 3524-3530
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
IDDQ,  SoC,  IFA,  parallel execution, 
  Summary |  Full Text:PDF (700.8KB)
A Fast Characterizing Method for Large Embedded Memory Modules on SoC
Masahiko OMURA  Toshiki KANAMOTO  Michiko TSUKAMOTO  Mitsutoshi SHIROTA  Takashi NAKAJIMA  Masayuki TERAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4  pp. 815-822
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
characterization,  memory compiler,  SoC,  LPE, 
  Summary |  Full Text:PDF (442.4KB)
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO  Tetsuya WATANABE  Mitsutoshi SHIROTA  Masayuki TERAI  Tatsuya KUNIKIYO  Kiyoshi ISHIKAWA  Yoshihide AJIOKA  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3463-3470
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
SoC,  interconnect,  physical parameter,  low-k,  capacitance,  resistance,  layout parasitic extraction, 
  Summary |  Full Text:PDF (593.7KB)
A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays
Hiroshi SHIROTA  Satoshi SHIBATANI  Masayuki TERAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/20
Vol. E80-A  No. 3  pp. 506-513
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
multilayer routing,  layout,  CAD,  VLSI, 
  Summary |  Full Text:PDF (749.4KB)