IEICE SEARCH SYSTEM

Masayuki MIZUNO

A Duobinary Signaling for Asymmetric Multi-Chip Communication Koichi YAMAGUCHI Masayuki MIZUNO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 619-626 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: partial response, Duobinary signaling, symbol-rate clock recovery, oversampled equalizer,
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Dicode Partial Response Signaling over Inductively-Coupled Channel Koichi YAMAGUCHI Masayuki MIZUNO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 613-618 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: inductively coupled, partial response, current-mode driver, adaptive equalization,
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A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests Shunichi KAERIYAMA Mikihiro KAJITA Masayuki MIZUNO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/01/01 Vol. E94-C No. 1 pp. 102-109 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock generator, duty ratio, frequency synthesis, I/Q balance, jitter, timing margin,
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LSI On-Chip Optical Interconnection with Si Nano-Photonics Junichi FUJIKATA Kenichi NISHI Akiko GOMYO Jun USHIDA Tsutomu ISHI Hiroaki YUKAWA Daisuke OKAMOTO Masafumi NAKADA Takanori SHIMIZU Masao KINOSHITA Koichi NOSE Masayuki MIZUNO Tai TSUCHIZAWA Toshifumi WATANABE Koji YAMADA Seiichi ITABASHI Keishi OHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/02/01 Vol. E91-C No. 2 pp. 131-137 Type of Manuscript: Special Section PAPER (Special Section on Silicon Photonics Technologies and Their Applications) Category: INVITED Keyword: optical interconnect, LSI, Si nano-photonics, SiON waveguide, Si nano-photodiode, surface plasmon antenna, TIA-less optical clock circuit,
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Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 829-835 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Analog and Communications Keyword: low power, daisy chain, inductive coupling, wide bandwidth,
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Solid-Electrolyte Nanometer Switch Naoki BANNO Toshitsugu SAKAMOTO Noriyuki IGUCHI Hisao KAWAURA Shunichi KAERIYAMA Masayuki MIZUNO Kozuya TERABE Tsuyoshi HASEGAWA Masakazu AONO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1492-1498 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: INVITED Keyword: solid-electrolyte, electrochemical reaction, ion diffusion, programmable logic,
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A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges Koichiro MINAMI Masayuki MIZUNO Hiroshi YAMAGUCHI Toshihiko NAKANO Yusuke MATSUSHIMA Yoshikazu SUMI Takanori SATO Hisashi YAMASHIDA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 220-228 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: delay-locked loop, infinite phase capture ranges, variable delay line, dynamic phase detector,
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Device-Deviation Tolerant Elastic-Vt CMOS Circuits with Fine-Grain Power Control Capability Masayuki MIZUNO Hitoshi ABIKO Koichiro FURUTA Isami SAKAI Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/20 Vol. E81-C No. 9 pp. 1463-1472 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: low-threshold voltage, leakage current, supply-voltage fluctuation, supply-voltage control, low power dissipation,
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A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO Masayuki MIZUNO Koichiro FURUTA Takeshi ANDOH Akira TANABE Takao TAMURA Hidenobu MIYAMOTO Akio FURUKAWA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1560-1571 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: phase-locked loop, low voltage, low jitter, fast-lock time,
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Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI Tomofumi IIMA Masayuki MIZUNO Tadahiko HORIUCHI Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/20 Vol. E79-C No. 7 pp. 942-947 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Interface Circuits Keyword:
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