Masato NAKAZATO

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Masato NAKAZATO  Michiko INOUE  Satoshi OHTAKE  Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 763-770
Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
software-based self-test,  processor,  test program template,  design for testability,  error masking,  at-speed testing, 
  Summary |  Full Text:PDF (521.6KB)
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
Masato NAKAZATO  Satoshi OHTAKE  Kewal K. SALUJA  Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 296-305
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
sequential circuit,  test generation,  synthesis for testability,  finite state machine,  test knowledge, 
  Summary |  Full Text:PDF (643.4KB)